International Business Machines Corporation

Florian Braun

Andreas Brodt

Daniel Martin

Oliver Schiller

Manuel Beck

Marvin Von Der Ehe

Lukas Dällenbach

Heinz Josef Hemmes

Zhong-Xiang He

Kai D Feng

Hanyi Ding

Xuefeng Liu

Michael V Koch

Howard Smith Landis

Matthias Ringe

Thomas Pflueger

Andreas Arp

Ulrich Weiss

Jesse Peter Surprise

Lukas Daellenbach

Guenther Hutzl

Geoffrey Woodhouse

Dedric Lichtenau

A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Placement and timing aware wire tagging

There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Enabling automatic staging for nets or net groups with VHDL attributes

A method for processing a database query on a database system includes receiving the database query at the database system, determining a sequence of database operations for processing the database query, estimating a number of incoming data elements of the database system to be processed for each of the database operations, estimating a workload of a programmable integrated circuit of the database system for each of the database operations based on the estimated number of incoming data elements, assuming each of the database operations is performed in a single instantiation, selecting a number of instantiations Nfor a database operation i of the sequence of database operations based on the estimated workload of the programmable integrated circuit for the database operation i, and configuring the programmable integrated circuit to execute the determined sequence of database operations, the database operation i is instantiated Ntimes.

Processing a database query in a database system

A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.

Timing based net constraints tagging with zero wire load validation

A computer identifies a metal layer, in a design, which contains routing track segregated by blockages. The sections of segregated routing track are removed and new routing track are added along the periphery of the blockage. It is determined if contact can be created between the component and the new routing track with the addition of a vertical interconnect access (VIA) structure. If contact can be created, then the VIA structures are added to create contact. If no contact can be created then another new routing track is added with (VIA) structures such that contact is created. Further routing track and VIA structures are added to higher metal layers to form a connection between a routing terminus located on a top metal layer and the new routing track and component.

Automation of interconnect and routing customization

Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.

Increased power line noise immunity in IC using capacitor structure in fill area

The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals

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Stuttgart, Germany

Florian Braun