Freescale Semiconductor,inc.

Bayerische Motoren Werke Aktiengesellschaft

Gm Global Technolgoy Operations, Inc.

Robert Boschgmbh

Daimler Chrysler Ag

Other

Koninklijke Philips Corporation N.v.

Motorola Corporation

Nxp B.v.

Nxp Usa, Inc.

Freescale Seimconductor, Inc.

Florian Bogenberger

Christopher Temple

Mathias Rausch

Vladimir Litovtchenko

Thomas Wuerz

Florian Hartwich

Thomas M Forest

Peter Fuhrmann

Robert Hugel

Christian Ebner

Manfred Bruno Zinke

Martin Peller

Bernd Elend

Josef Berwanger

Bernd Müller

Harald Eisele

Arnold W Millsap

Anton Schedl

Ralf Belschner

Jörn Ungermann

Bernd Hedenetz

Oleksandr Sakada

Harald Weiler

Peter Lohrmann

Thomas Führer

Patrick Willem Heuts

Matthias Kühlewein

James B Eifert

Manfred P Thanner

Jehoda Refaeli

Anthony M Reipold

Joachim Kruecken

Leos Chalupa

Alexander Maier

Davor Bogavac

Max Turner

Gregor Pokorny

Leonard Link

Emily Hudoletnjak

Joaquim Kruecken

A method for validating a time function in a network of a vehicle includes: ascertaining a receiving time of a sync message of a master; receiving a follow-up message of the master; ascertaining a receiving time of a further sync message of the master; receiving a further follow-up message of the master; determining a time function of the first client based on the receiving time of the sync message, the receiving time of the further sync message, the transmission time of the follow-up message, and the transmission time of the further follow-up message; ascertaining a synchronized transmission time of a path delay request message from the first client to the master; ascertaining a synchronized receiving time of a path delay response message from the master; receiving a path delay response follow-up message from the master by the first client; and validating a time function of the master.

Method, computer-readable medium, system, and vehicle comprising the system for validating a time function of a master and the clients in a network of a vehicle

An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request. The control logic unit may be arranged to determine whether the received request belongs to the current state of the processor, to grant the request when the received request does belong to the current state and to reject the request in case the request does not belong to the current state. The control logic unit may further include a control logic output for outputting an request grant signal when the request is granted.

Request controller, processing unit, arrangement, method for controlling requests and computer program product

A display controller includes a controller input connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display and to receive second image data representing a safety relevant part of the image. A merging unit is connected to the controller input, for composing the image from the first image data and second image data. A controller output is connectable to the display, for outputting display data representing the image. An image monitor is connected to the controller output, for comparing a part of the image corresponding to the safety relevant part with an reference for the part.

Display controller, image processing system, display system, apparatus and computer program product

A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine.

Timer unit, system, computer program product and method for testing a logic circuit

A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.

Synchronization of stateful elements in a processing resource using a scan chain

A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.

Resource allocation within multiple resource providers based on the incoming resource request and the expected state transition of the resource requesting application, and selecting a resource provider based on the sum of the percentage of the resource provider currently used, the requesting load as a percentage of the resource provider's total resource, and the additional load imposed by the expected state of the requesting application as a percentage of the resource provider's total resource

A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.

Data processing system, data processing method, and apparatus

A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value. The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.

Request controller, processing unit, method for controlling requests and computer program product

A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyze internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and at least one further signal processing logic module.

Method and apparatus for handling an output mismatch

A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit, data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.

System, computer program product and method for testing a logic circuit

A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to the master clocks. The synchronization system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronization data source for generating slave clock synchronization data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronization data source. The time-base controller may receive the slave clock synchronization data and control one or more of the one or more slave clocks in accordance with the slave clock synchronization data.

Network and method for setting a time-base of a node in the network

A multi-node communications system is provided with communications protocol using both static () (pre-determined) and dynamic (. . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (. . . ) and the dynamic (. . . ) communication slots. Each node includes a synchronized time basemade up of consecutive timeslots (. . . ). The timebasehas substantially the same error tolerance in each node. For static communication (), a predetermined number of timeslots () are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots () are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern. Communication jitter is well defined and dealt with, and large oscillator drifts are compensated for.

System node and method for providing media arbitration

A data communication network may include two or more master clocks, and a synchronization system connected to the master clocks. The synchronization system may determine a time-base for the master clocks. The synchronization system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.

A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.

Error detector in a cache memory using configurable way redundancy

The invention refers to a method for monitoring a communication media access schedule of a communication controller () of a communication system () by means of a bus guardian (). The communication system () comprises a communication media () and nodes () connected to the communication media (). Each node () comprises a communication controller () and a bus guardian () assigned to the communication controller (). Messages are transmitted among the nodes () across the communication media () based on a cyclic time triggered communication media access scheme. In order to provide a mechanism which allows the bus guardian () to monitor the communication media access scheme of the communication controller () even during startup of the communication it is suggested, that the bus guardian () has a priori knowledge about possible deviations from the communication media access schedule during startup of the communication and that the bus guardian () during startup makes use of the a priori knowledge to distinguish between an allowed deviation and a forbidden deviation caused by a failure of the communication controller ().

Method for monitoring a communication media access schedule of a communication controller of a communication system

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Poing, Germany

Florian Bogenberger