Stmicroelectronics S.a.

Florent Vautrin

Richard Ferrant

Francois Jacquet

Fran&ccedil;ois Jacquet

A memory circuit includes a plurality of storage cells () arranged in rows and columns thus forming a storage matrix. The storage cells () corresponding to the same bit line (-) are divided into several groups (-) of cells for the same column, these groups having their own biasing circuit () in order to act on the difference between the logic level low voltage and the substrate voltage of the link transistors. When a storage cell is not selected, the biasing circuit makes the voltage between source/drain and substrate equal to a negative voltage in order to minimize the leakage current. During a read operation, the substrate voltage and the source/drain voltage are brought back to the same level such that a maximum current will flow when the link transistor is conducting.

Memory with storage cells biased in groups

A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

DRAM cell refreshment method and circuit

A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Growing community of inventors

Vizille, France

Florent Vautrin