Arm Limited

Florent Begon

Nicolas Chaussade

Jocelyn Francois Orion Jaubert

Philippe Luc

Elodie Charra

Melanie Emanuelle Lucie Teyssier

Norbert Bernard Eugene Lataille

Cédric Denis Robert Airaud

Chris Abernathy

Natalya Bondarenko

Philippe Jean-Pierre Raphalen

Norbert Bernard Eugéne Lataille

Michael Filippo

Guillaume Bolbenes

Frederic Claude Marie Piry

Houdhaifa Bouzguarrou

Vladimir Vasekin

Thibaut Elie Lanois

Gilles Eric Grandou

Rémi Marius Teyssier

Lucas Garcia

Damien Guillaume Pierre Payet

Nathanael Premillieu

Nicolas Jean Phillippe Huot

Mélanie Emanuelle Lucie Teyssier

Frederic Claude Piry

Mélanie Vincent

Melanie Emanuelle Lucie Vincent

Pierre Marcel Laurent

Andrew Christophe Rose

Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

Methods and apparatus for predicting instructions for execution

There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.

Increasing effective cache associativity

Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry. The apparatus comprises a plurality of prefetch units, each prefetch unit being associated with a cache level and being arranged to prefetch data into the associated cache level in anticipation of the processing circuitry requiring the data, wherein: each cache level has a plurality of entries and is arranged to maintain prefetch tag information for each entry which, when a given entry contains prefetched data, indicates which prefetch unit of that cache level and/or of a lower cache level prefetched that data; and each cache level is arranged, responsive to a data request from a higher cache level, to provide to the higher cache level the requested data and the prefetch tag information corresponding to the requested data. The apparatus further comprises accuracy information storage to: maintain accuracy inferring information for each prefetch unit; and when given data is evicted from a cache level, update the accuracy inferring information based on the prefetch tag information.

Methods and apparatus for monitoring prefetcher accuracy information using a prefetch flag independently accessible from prefetch tag information

An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.

Handling move instructions via register renaming or writing to a different physical register using control flags

A single threaded out-of-order processorincludes an architected register fileand a speculative register file. Speculative register allocation circuitryserves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitryserves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitryserves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.

Speculative register file read suppression

A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.

Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state

A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.

Apparatus and method for predicting target storage unit

A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.

Data processing apparatus and method for converting data values between endian formats

Checkpointing long latency instruction as fake branch in branch prediction mechanism

A data processing systemis provided with multiple processor coreseach incorporating a data cache memory. A snoop control unitmanages coherency between the data values stored within the data caches. The snoop control unitincorporates a TAG memory. If an error is detected within an entry of the TAG memory, then a hit operation is forced to the corresponding storage location one or more of the data caches

Error handling mechanism for a tag memory within coherency control circuitry

Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value.

Control of clock gating

A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2) transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

Cache eviction

Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to a single instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Suppressing register renaming for conditional instructions predicted as not executed

A processorutilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channelfor further processing. The remaining set are performed in sequence with the results being passed via a background channelfor further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

Method for renaming a large number of registers in a data processing system using a background channel

A data processing apparatussupports out-of-order processing register renaming using a renaming stage. A set of physical registersis mapped to architectural registers. Available-register identifying logicis used to identify which physical registersare available for use by the renaming stage. The available-register identifying logicincludes an instruction FIFOstoring register mapping data for unresolved instructions and indicating physical registersstoring data values which may be required in association with those unresolved speculative instructions. The speculative instructions may be predicted branch instructions, load/store instructions, conditional instructions or other types of instruction.

Growing community of inventors

Antibes, France

Florent Begon