Allegro Microsystems, LLC

Florencia Ferrer

Lucas Intile

Jesse Lapomardo

Nicolás Rigoni

Andreas P Friedrich

Juan Manuel Cesaretti

Emanuele Andrea Casu

Cédric Gillet

Emil Pavlov

Lautaro Casella

Sergio Nicolás Deligiannis

A sensor integrated circuit (IC) includes a sensing element configured to sense a parameter associated with a target, a processor coupled to the sensing element and configured to generate a sensed signal indicative of the parameter associated with the target, and an output module coupled to receive the sensed signal. The output module is configured to transmit absolute data on a message line at a first rate and transmit incremental data on one or more index lines at a second rate, wherein the second rate is faster than the first rate, wherein the incremental data comprises data associated with changes in the absolute data and wherein an edge or a pulse is used to indicate an incremental change has occurred in the absolute data.

Sensor signaling of absolute and incremental data

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Oscillator monitoring circuits for different oscillator domains

A sensor includes a sensing element to produce a sensing element signal and a processor responsive to the sensing element signal to generate a sensor output signal comprising a Single Edge Nibble Transmission (SENT) frame. The SENT frame includes a Status and Communication (SCN) nibble comprising a bitand a bitthat represent a status of at least one internal diagnostic indicator and a plurality of data nibbles. At least one of the plurality of data nibbles includes a cyclic redundancy check (CRC), the CRC being an encoding of the bitand the bitof the SCN nibble and the plurality of data nibbles and at least one of the plurality of data nibbles includes a count that indicates a new frame, the CRC being at least a five bit value.

Sensor integrated circuits having a single edge nibble transmission (SENT) output

In one aspect, a magnetic field sensor includes a magnetic field sensing element configured to detect changes in a magnetic field caused by a target and an encoder configured to process signals originating from the magnetic field element. The encoder is configured to generate a first output signal and a second output signal. In a non-fault state, the first and second output signals are 90 electrical degrees out of phase from one another, and in a fault state, the first and second output signals are in phase with each other.

Magnetic field sensor with fault reporting

A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

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Montevideo, Uruguay

Florencia Ferrer