Intel Corporation

Agilent Technologies, Inc.

Florence Eschbach

Fu-Chang Lo

Alexander Tregub

Paul A Zimmerman

Shawming Ma

James M Powers

Gary William Ray

Susan M Holl

Alexander (Alex) Tregub

A pellicle membrane is mounted between an outer frame and an inner frame. At least one of the frames is attached to the reticle without using conventional adhesives. The pellicle and reticle may be used in a lithography system. The pellicle allows radiation to pass through the pellicle to the reticle and may prevent particles from passing through the pellicle.

Mounting a pellicle to a frame

An embodiment of the present invention includes a technique to improve stability of a pellicle. The pellicle is pre-baked at a predetermined temperature substantially below a glass transition temperature. The pre-baked pellicle is purged with an inert gas. The purged pellicle is radiated by a radiation at a wavelength. In another embodiment, a chamber is sealed with a pellicle membrane which divides the chamber into first and second compartments. The chamber has an inflow opening in the first compartment and an outflow opening in the second compartment. A gas is injected into the inflow opening and penetrates the pellicle membrane to the outflow opening. In another embodiment, the chamber has first inflow and outflow openings and second inflow and outflow openings in the first and second compartments, respectively. A first gas is injected into the first inflow opening and a second gas into the second inflow opening. The first and second gases have a permeability difference. The first gas penetrates the pellicle membrane to the second outflow opening.

Radiation stability of polymer pellicles

Disclosed are pellicle compositions and methods of making such pellicle compositions. The pellicle compositions provided include highly fluorinated polymers as well as fluorinated polymer/PVDF co-polymers.

Process to optimize properties of polymer pellicles and resist for lithography applications

Attaching a pellicle frame to a reticle

A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST). The electrode plates and the capacitor dielectric are formed by depositing layers of appropriate materials within the cavity, which has been formed to include tapering walls in a dielectric layer of the layer stack. Next, portions of the deposited layers, or a &ldquo;capacitor stack,&rdquo; are removed down to the surface of the dielectric layer such that only the materials that were deposited within the cavity of the dielectric layer are left. The remaining materials form the electrode plates, as well as the capacitor dielectric. In the preferred embodiment, the selective removal of the capacitor stack portions is accomplished by planarizing the capacitor stack using a Chemical Mechanical Planarization (CMP) process. Alternatively, a sputter etch-back process may be utilized to remove the capacitor stack portions.

Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell

Growing community of inventors

Portola Valley, CA, United States of America

Florence Eschbach