Sgs-Thomson Microelectronics S.r.l.

Flavio Scarra

Virginia Natale

Gianluca Petrosino

Maurizio Giovanni Gaibotti

Alberto Taddeo

Giuseppe Meroni

Angelo Moroni

Siro M Morganti

Giampiero Trupia

A method for loading the content of any selected cell of a source register to any selected cell of a destination register. The value in the selected source cell is tested for a value of zero. The value of the destination register is then copied into a temporary register. During the copying, the selected destination cell is set to a selected value. The selected destination cell, in the temporary location, is either left unchanged or reset to a complementary value depending on the result of the previous zero test. In either event, the value of the temporary register is then copied to the destination register.

Method for carrying out a boolean operation between any two bits of any

A circuit for generation of a reset signal in an electronic device, of the type comprising a microprocessor interlocked with a circuit generating a clock signal and memories of both the volatile type and the non-volatile type, is capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor.

Circuit for detecting a fault state in a clock signal for microprocessor

A process for checking, reading or writing memories of a programmed computer. The process selects a pre-selected logic space in a memory to be checked. The process triggers the addressing micro-instructions of a suitable micro-program related to a pre-selected checking procedure, so as to cause its execution by means of a pre-established number of clock strokes. The micro-instructions of the micro-program are executed according to an incremental sequence and repeated in a loop.

Process for checking the memories of a programmed microcomputer by means

The probability of soft-programming of the reference cells of a FLASH-EPROM memory may be excluded by having a decoupling transistor of a type of conductivity opposite to that of the cells functionally connected between the gate of each reference cell and the respective row line. Moreover the elimination of the electrical stresses to which the reference cells are subjected during the repeated programming cycles of the memory cells, increases the stability of the respective reference values of threshold and current level provided by the reference cells, thus increasing the reliability of the device.

FLASH-EPROM with enhanced immunity from soft-programming of reference

Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of the first level of metal and the relative secondary source line patterned in the second metal layer. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.

Bank erasable, flash-EPROM memory

The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).

Monostabilized dynamic programmable logic array in CMOS technology

The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

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Agrate Brianza, Italy

Flavio Scarra