Stmicroelectronics N.v.

Ikanos Communications, Inc.

Velocity Communication, Inc.

Stmicroelectronics Gmbh

Firooz Massoudi

Behrooz Rezvani

Avadhani Shridhar

Sam Heidari

Raminder Singh Bajwa

Omprakash S Sarmaru

Masoud Eskandari

T R Ramesh

Tiruvur R Ramesh

Sridhar Begur

Omprakash S Samaru

A convolutional decoder for a wired or wireless receiver receiving an encoded datastream. The branch and path metric components compute branch and path metrics for the encoded datastream stream. The traceback unit couples to the path metric component to trace in each traceback interval a single path through the path metrics to determine correction factors for decoding at least two corresponding successive sub-symbols/symbols from the encoded datastream in each traceback interval.

Method and apparatus for forward error correction

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Method and apparatus for a X-DSL communication processor

A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.

Method and apparatus for providing packet based and distributed xDSL communications

The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

Method and apparatus for synchronizing a packet based modem supporting multiple X-DSL protocols

Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Device and method for detecting synchronization patterns in CD-ROM media

A device for detecting and correcting errors in error correction coded (ECC) data blocks that are read sequentially from a DVD medium is disclosed. Each ECC data block is defined as a two dimensional block of a plurality of columns and rows. Each of the ECC data blocks is read from the DVD medium sequentially in rows. The device includes row correction circuitry, a buffer, column correction circuitry, and repeat correction circuitry. The row correction circuitry is configured to sequentially receive the rows of an ECC data block for detecting and correcting up to a first predetermined number of errors in each of the received rows. The buffer is coupled to the row correction circuitry for receiving the error corrected rows of the ECC data block as a receiving buffer. The buffer also stores the ECC data block as a correction buffer when all the rows of the ECC data block have received. The column correction circuitry is coupled to the row correction circuitry and the buffer to sequentially receive the row error corrected rows of the ECC data block for detecting the uncorrected errors. The column correction circuitry is also configured to correct the uncorrected errors in the columns of the ECC data block that is stored in the correction buffer. The repeat correction circuitry is coupled to the buffer for detecting and correcting the remaining uncorrected errors in the correction buffer.

Device and method for decoding data streams from storage media

Disclosed is a device for performing a header and row correction on rows of sector data that are read sequentially from a DVD medium. The device includes a pair of row buffers, a syndrome generator, and an error correction circuitry. The pair of row buffers sequentially receives and stores a current row of the sector data. When one buffer is receiving a next row of the sector data and is functioning as a receive buffer, the other buffer stores the current row of the sector data and functions as a correction buffer to be used in error correction. The syndrome generator receives the current row of the sector data and is configured to sequentially generate a row syndrome for the current row. The row syndrome is configured to indicates whether an error is present in the current row that is stored in the correction buffer. The error correction circuitry is coupled to the syndrome generator and is configured to receive the row syndrome associated with the current row that is stored in the correction buffer. The error correction circuitry is configured to correct the error that is present in the current row that is contained in the correction buffer.

Growing community of inventors

Santa Clara, CA, United States of America

Firooz Massoudi