Fujitsu Corporation

Micron Technology Incorporated

Virtensys Limited

International Computers Limited

Xyratex Technology Limited

Finbar Naven

Marek Piekarski

Peter L Desyllas

Stephen John Marshall

Ian David Johnson

Jose Duato

John Roger Drewry

Jose Flich

Nicholas Peter Holt

Paul Howarth

Antony Sou

Wayne Eric Rashman

Mark Piekarski

Simon Timothy Smith

Paul Barnes

Stuart G Hale

A method for transmitting data packets from a first device through a switch to a second device is described. The method is performed at an intercepting device intermediate the first device and the switch device. The method comprises receiving a first data packet from the first device, determining that the first data packet is to be transmitted to the second device and determining whether the first data packet is of a first type that can not be transmitted from the intercepting device to the second device through the switch. If the first data packet is of the first type, the first data packet is encapsulated within a second data packet and transmitting the second data packet through the switch to the second device. If the first data packet is not of the first type, the method comprises transmitting the first data packet through the switch to the second device.

Encapsulation enabled PCIE virtualisation

A method for providing identifiers for virtual devices in a network. The method comprises receiving a discovery data packet directed to a physical network node associated with a physical endpoint device. A response to the discovery data packet directed to a physical network node is provided, the response comprising an identifier of a virtual device. At least one further discovery data packet directed at least to said virtual device is received. A response to a first one of the further discovery data packets is provided, the response comprising an identifier of a virtual endpoint device. At least some functionality of the virtual endpoint device is provided by the physical endpoint device.

Switching method

There is herein described a method for transmitting data packets from a first device through a switch to a second device. The method is performed at an intercepting device intermediate the first device and the switch device. The method comprises receiving a first data packet from the first device, determining that the first data packet is to be transmitted to the second device and determining whether the first data packet is of a first type that can not be transmitted from the intercepting device to the second device through the switch. If it is determined that the first data packet is of the first type, the method comprises encapsulating the first data packet within a second data packet, the second data packet being of a second type that can be transmitted from the intercepting device through the switch to the second device, and transmitting the second data packet through the switch to the second device. If it is determined that the first data packet is not of the first type, the method comprises transmitting the first data packet through the switch to the second device.

A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.

Data switch

A method of processing data packets, each data packet being associated with one of a plurality of entities. The method comprises storing a data packet associated with a respective one of said plurality of entities in a buffer, storing state parameter data associated with said stored data packet, the state parameter data being based upon a value of a state parameter associated with said respective one of said plurality of entities, and processing a data packet in said buffer based upon said associated state parameter data.

Queue processing method

A switch for connection in a network of other like switches and includes memory for storing data packets, a control system arranged to control the switch to, upon receipt at one of the ingress or egress ports of notification of congestion at a downstream congested port, either store at said ingress port or egress port data packets received for said congested port or to communicate with an upstream port for storage at said upstream port of data packets destined for the congested port, and in dependence on the current of stored data, to send a message to a further upstream port informing the further upstream port of the congestion downstream. The memory is provided substantially only at the ingress ports or the egress ports of the switch.

Method for congestion management of a network, a switch, and a network

A method of congestion management within a switch or network of connected switches is provided, wherein the or each of the switches has a plurality of ingress ports and a plurality of egress ports. The method involves, when congestion is detected at a first ingress or egress port, sending a message to an upstream port connected to the first ingress or egress port indicating that congestion has occurred at a particular port and requesting storage at the upstream port of data packets destined for that port; and, in dependence on the amount of data packets destined for the congested port stored at the upstream port, sending from the upstream port to a further upstream port a message informing the further upstream port of the congestion at the congested port, the further upstream port storing at the further upstream port data packets destined for the congested port.

Method for congestion management of a network, a signalling protocol, a switch, an end station and a network

A method of queuing data packets, said data packets comprising data packets of a first packet type and data packets of a second packet type. The method comprises grouping received packets of said first and second packet types into an ordered series of groups, each group comprising at least one packet, maintaining a group counter indicating the number of groups at the beginning of the series of groups comprising only packets of the second packet type, and transmitting a packet. A packet of the second packet type is available for transmission if but only if the group counter is indicative that the number of groups at the beginning of the series of groups comprising only packets of the second packet type is greater than zero.

Queuing method

A switching device comprising at least one ingress port and at least one egress port. The switching device is arranged to receive data packets through the at least one ingress port and to forward received data packets to respective ones of the at least one egress port. The switching device further comprises a primary buffer arranged to store data packets received via at least one of the least one ingress ports and a secondary buffer associated with the primary buffer. The switching device is adapted to select a data packet from the primary buffer and if but only if the secondary buffer satisfies a least one first predetermined criterion, transfer the selected data packet to the secondary buffer.

Switching device

A method of switching data packets between an input and a plurality of outputs of a switching device. The switching device comprises a memory arranged to store a plurality of data structures, each data structure being associated with one of said outputs. The method comprises receiving a first data packet at said input, and storing said first data packet in a data structure associated with an output from which said data packet is to be transmitted. If said first data packet is intended to be transmitted from a plurality of said outputs, indication data is stored in each data structure associated with an output from which said first data packet is to be transmitted, but said first data packet is stored in only one of said data structures. The first data packet is transmitted from said data structure to the or each output from which the first data packet is to be transmitted.

Multicast data packet switching method

A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through the ingress ports and to forward received data packets to respective ones of the egress ports. The switching device further comprises an ingress module for each of the ingress ports, each ingress module being arranged to receive data packets from a respective single one of the ingress ports and to store the received data packets in one of a plurality of data structures provided by the ingress module, each ingress module being further configured to select a data packet from one of the plurality of data structures, and to request permission to transmit the selected data packet to an egress port. The switching device also comprises at least one egress module arranged to receive a plurality of requests for permission to transmit data packets through a particular egress port, the request being generated by the plurality of ingress modules, and to select one of the plurality of requests.

A first transparent latch receives a first synchronised signal changing its logic state synchronously with respect to a clock signal. A second transparent latch receives a second synchronised signal output by the first latch. When the clock signal has a first logic state the first latch has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state the first latch has the responsive state and the second latch has the non-responsive state. The change in logic state of a third synchronised signal output by the second latch is guaranteed to occur in a particular half-cycle of the clock signal, irrespective of process/voltage/temperature (PVT) variations of the circuitry. Clock recovery circuitry may have rising-edge and falling-edge latches; circulating control pattern verification circuitry; data synchronising circuitry for converting parallel data clocked by a first clock signal into serial data clocked by a second clock signal asynchronous with the first clock signal; and data recovery circuitry for producing an offset clock signal which suits a data eye shape of a received serial data stream.

Processing high-speed digital signals

In a semiconductor integrated circuit device () in which variation in a minimum propagation time of a transmission signal from a source node (SN) to a destination node (DN) is sufficiently large, relative to a clock period (T) at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node (DN) a plurality of clocked elements (to) are connected in series between the source and destination nodes for causing a shift signal (SSto SS), representing the transmission signal present at the source node (SN) in a first clock cycle, to be shifted from the source node (SN) to the destination node (DN) through the series of clocked elements (to) one clocked element () per predetermined number of clock cycles. The series of clocked elements (to) is connected and arranged such that variation (v) in a propagation time of the shift signal (SS) from one clocked element () to the next clocked element () is sufficiently small, relative to the clock period (T), that a clock cycle in which the shift signal (SS) reaches the next clocked element () does not vary, whereby the shift signal (SS) always reaches the destination node (DN) a fixed number of clock cycles after the first clock cycle.

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Cheshire, United Kingdom

Finbar Naven