Stmicroelectronics S.r.l.

Texas Instruments Corporation

Roelectronics S.r.l.

Filippo Marino

Salvatore Giombanco

Salvatore Vincenzo Capici

Salvatore Tumminaro

Giovanni Lombardo

Marco Minieri

Angelo Maria D'Arrigo

Seetharaman Sridhar

Francesco Pulvirenti

Joseph Michael Leisten

Eliana Cannella

Sameer P Pendharkar

Philip Leland Hower

Yongxi Zhang

Rosario Davide Stracquadaini

Michael Ryan Hanschke

Michele Grande

Giuseppe Maria Di Blasi

Claudio Adragna

Richard Lee Valley

Sunglyong Kim

Bharath Balaji Kannan

Ignazio Salvatore Bellomo

Tobin D Hagan

Ananthakrishnan Viswanathan

Paolo Sandri

Antonio Magazzu

John Christian Vogt

Salvatore Pappalardo

Andrea Rapisarda

Alessandro Camera

Antonio Amoroso

Gaetano Petrina

Valeria Boscaino

Giovanni Genco Russo

Pietro Costanza

Vincenzo Campo

In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.

Power factor correction boost converter having an on-time responsive to negative current

In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.

Boost power factor correction conversion

In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.

Multi-mode high voltage circuit

A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal.

Monitoring SMPS power switch voltage via switch drain source capacitance

An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

Integrated high-side driver for P-N bimodal power device

At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.

Hysteretic power converter controller

A circuit for use in an LLC converter to control diode conduction time includes a secondary side controller, the secondary side controller configured to monitor voltage, measure a diode conduction time for the LLC converter, in response to determining that the diode conduction time is greater that a target time, increase the on-time for the first switch, and in response to determining that the diode conduction time is less than a target time, decrease the on-time for the first switch.

LLC secondary side control with adaptive on-time

Peak current in a switching converter is controlled using a closed loop to compensate for error caused by delay time in the switching transistor and control logic. A reference value is established that represents a target current value. A compensated reference value is derived from the reference value by the closed loop. A periodic inductor current is formed in the switching converter in response to the compensated reference value. An error signal is formed that is indicative of an amount of time the inductor current exceeds the target current value. The compensated reference value is dynamically adjusted by the compensation closed loop to minimize the error signal.

Adaptive driver delay compensation

A receiver of a signal communication apparatus; the apparatus including a transmitter adapted to transmit coded signals, the receiver for receiving the signal and a wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver includes a decoder configured to decode the received signal and circuitry coupled to the receiving antenna and capable of triggering the decoder if the value of the received signal is outside a logical hysteresis having a first logic threshold having a value smaller than the value of the direct current component of the received signal and a second logic threshold having a value greater than the value of the direct current component of the received signal.

Receiver for signal communication apparatus and related signal communication apparatus

A receiver of a signal communication apparatus; the apparatus having a transmitter for transmitting the signals, the receiver for receiving the signals and a galvanically isolated wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver including a disturbance rejection circuit coupled to the receiving antenna and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Receiver for signal communication system with disturbance rejection circuit

A transmission and reception apparatus includes a transmitter, a receiver and a galvanically isolated interface arranged between the transmitter and the receiver. The transmitter, receiver and interface are arranged so as to form a two-level isolated digital channel and the transmitter includes a block adapted to send a clock signal to the receiver. The receiver includes a circuit adapted to synchronize the receiver and the transmitter using the received clock signal and a circuit adapted to memorize information related to the synchronization in a storage element to hold the synchronization while the receiver is receiving the digital data. The transmitter block is adapted to send the digital data signal after the synchronization of the receiver and transmitter.

Transmission and reception apparatus for digital signals

A signal communication apparatus comprising first and second channels for communicating signals between two electronic devices; each of said first and second channels has a transmitter for transmitting signals, a receiver for receiving signals and an interface arranged between the transmitter and the receiver. The transmitters code the signals in the form of a frame of H bits, with H being an integer, and adapted to serially transmit said frame of H bits through said interface, and the receivers decode the frames of H bits, a frame of H bits having P data bits, K redundancy bits and a sequence of L control bits adapted to identify the type of frame to be transmitted, with L, P and K being integers.

Signals communication apparatus

A device for measuring the current flowing through a power transistor of a voltage regulator, the voltage regulator having an input voltage and providing a regulated output voltage and the power transistor coupled between the input and output voltages. The measuring device includes a further transistor adapted to mirror a portion of the current flowing through the power transistor, the further transistor and the power transistor have a first non-drivable terminal in common that is coupled to the input voltage. The measuring device also includes a circuit block to connect the second non-drivable terminals of the power and the further transistor and to provide an output current equal to the portion of the current flowing through the first transistor; the measuring device further including a circuit adapted to detect the output current of said circuit block.

Device for measuring the current flowing through a power transistor of a voltage regulator

A DC-DC converter including: a switch, having a control terminal receiving a control signal, and a conduction terminal supplying a current; a load, coupled to the conduction terminal of the switch and selectively receiving the current; a control circuit, receiving a clock signal and generating the control signal in synchronism with the clock signal; an overcurrent sensor, coupled to the switch so as to monitor an electrical quantity correlated to the current and to output a protection signal in presence of overcurrent; moreover including overcurrent-protection circuitry, receiving the protection signal and the clock signal and generating a disabling signal for the control circuit if delay between an overcurrent detection and the clock signal is shorter than a detection time.

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Tremestieri Etneo, Italy

Filippo Marino