Em Microelectronic-marin Sa

Filippo Marinelli

Lubomir Plavec

David A Kamp

Thierry Roz

Tomas Novak

Miloslav Kubar

The present invention concerns an anti-tearing protection system () for a non-volatile memory () comprising a first memory block () and a second memory block (), the first and second memory blocks () being arranged to store a data set comprising user data and an error detection code obtained based on the user data. The first and second memory blocks () can be read in a first read mode for determining logic states of data elements comprised in the data set according to the first read mode. The user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value. The first and second memory blocks () can further be read in a second read mode for determining the logic states of the data elements comprised in data set according to the second read mode. The user data in a respective memory block are considered to be correct according to the second read mode if its error detection code equals the first given value and if the user data as read in the second read mode are determined to be identical to the user data as read in the first read mode. A third read mode may also be defined. The first read mode may be considered to be a normal read mode, while the second and third read modes may be used to determine if data were strongly written and erased, respectively.

Anti-tearing protection system for non-volatile memories

The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises

Regulation circuit for a charge pump and method of regulation

The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Electronic memory device and test method of such a device

A memory circuit is provided, including at least one bit cell configured to store data and having a first terminal and a second terminal, one of the terminals being coupled to a bit-line; at least one current switch connected to the bit-line and connected to a current source and being configured to selectively provide at least a read current to the bit cell; and a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is disposed between the bit cell and the at least one current switch.

Memory circuit including a current switch and a sense amplifier

The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Voltage regulator

The self-powered detection device comprises a Non-Volatile Memory (NVM) unit formed by at least a NVM cell and a sensor activated by a physical or chemical action or phenomenon, the NVM unit arranged for storing in the NVM cell, by using electrical power of the electrical stimulus pulse, a bit of information relative to detection by the sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal and a base terminal of the NVM unit with at least a given set voltage.

Self-powered detection device with a non-volatile memory

The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

Growing community of inventors

Lussy-sur-Morges, Switzerland

Filippo Marinelli