International Business Machines Corporation

Cornell University

Filipp A Akopyan

Dharmendra S Modha

John Vernon Arthur

Paul A Merolla

Andrew S Cassidy

Jun Sawada

Bryan L Jackson

Rajit Manohar

Alyosha C Molnar

Rodrigo Alvarez-Icaza Rivera

William P Risk, Iii

Pallab Datta

Steven Kyle Esser

Tapan K Nayak

Carlos O Otero

Michael V DeBole

Myron Dale Flickner

Rathinakumar Appuswamy

Brian Taba

Rodrigo Alvarez-Icaza

An event-driven neural network including a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array that has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

Neuromorphic event-driven neural computing architecture in a scalable neural network

Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

Neural network weight distribution from a grid of memory elements

Neural inference chips for computing neural activations are provided. In various embodiments, the neural inference chip is adapted to: receive an input activation tensor comprising a plurality of input activations; receive a weight tensor comprising a plurality of weights; Booth recode each of the plurality of weights into a plurality of Booth-coded weights, each Booth coded value having an order; multiply the input activation tensor by the Booth coded weights, yielding a plurality of results for each input activation, each of the plurality of results corresponding to the orders of the Booth-coded weights; for each order of the Booth-coded weights, sum the corresponding results, yielding a plurality of partial sums, one for each order; and compute a neural activation from a sum of the plurality of partial sums.

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.

Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency

Embodiments of the invention provide a system and circuit interconnecting peripheral devices to neurosynaptic core circuits. The neurosynaptic system includes an interconnect that includes different types of communication channels. A device connects to the neurosynaptic system via the interconnect.

Peripheral device interconnections for neurosynaptic systems

Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.

Memory-mapped interface to message-passing computing systems

An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

Memory-mapped interface for message passing computing systems

Embodiments of the invention relate to a neural network circuit comprising a memory block for maintaining neuronal data for multiple neurons, a scheduler for maintaining incoming firing events targeting the neurons, and a computational logic unit for updating the neuronal data for the neurons by processing the firing events. The network circuit further comprises at least one permutation logic unit enabling data exchange between the computational logic unit and at least one of the memory block and the scheduler. The network circuit further comprises a controller for controlling the computational logic unit, the memory block, the scheduler, and each permutation logic unit.

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Embodiments of the invention relate to a system for controlling program execution. The system comprises an event-based core controller including a set of state-preserving elements. The core controller starts and stops the program execution based on one or more control signals. For each instruction of the program, the core controller triggers a target component to execute the instruction by generating and sending an instruction and/or a trigger pulse to the target component.

Growing community of inventors

New Windsor, NY, United States of America

Filipp A Akopyan