Texas Instruments Corporation

Fikret Dulger

Nikolaus Klemmer

Satish V Uppathil

Robert Bogdan Staszewski

Gennady Feygin

Francis P Cruise

A front-end receiver includes a first mixer of a first channel, a second mixer of a second channel, and a switching circuit that is configured to select the first mixer or the second mixer during a particular time period. Upon being selected, one of the first mixer or the second mixer is configured to deliver a down-converted signal that down-converts a respective RF signal of either the first or second reception channel. As the tasks of down-conversion and multiplexing are combined at the mixer level, the first and second reception channels may share a baseband circuit while being able to provide a well-balanced metrics of channel isolation, low noise figure, and linearity.

Front-end transceivers with multiple reception channels

A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a common-source (CS) circuit stacks against a common-gate (CG) circuit. The CG circuit provides the input impedance matching while the CS circuit boosts the amplification gain. As a result, the disclosed amplifier allows the front-end receiver to break free from a tradeoff between input impedance matching and gain boosting. Moreover, the disclosed amplifier achieves power saving and noise reduction by having the CS circuit to share the same bias current with the CG circuit.

Front-end matching amplifier

A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.

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Plano, TX, United States of America

Fikret Dulger