Qualcomm Incorporated

Fifin Sweeney

Mario Francisco Velez

Milind Shah

Lew G Chua-Eoan

Zhi Zhu

Junmou Zhang

Jason R Gonzalez

Damion B Gastelum

Yuancheng Christopher Pan

Yuan-cheng Christopher Pan

Jason Gonzalez

Milind P Shah

A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

Integrated voltage regulator with embedded passive device(s) for a stacked IC

An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.

Microelectromechanical systems embedded in a substrate

In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Thermal vias in an integrated circuit package with an embedded die

A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.

Printed circuit board having embedded dies and method of forming same

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Fifin Sweeney