Bull Hn Information Systems Italia S.p.a.

Honeywell Information Systems Italia

Honeywell Bull Italia S.p.a.

Ferruccio Zulian

Aimone Zulian

Carlo Bagnoli

Vittorio Zanchi

Angelo Lazzari

Angelo Ramolini

Antonio Brioschi

Computer system comprising a communication bus, a plurality of units connected to the bus, in which the bus includes a plurality of bus segments, each bus segment being concatenated with at least one adjacent bus portion by means of buffer registers to transfer a data item from the adjacent bus segment to the bus portion, the computer system further comprising an arbitration unit to control, for each bus segment, the simultaneous access to the different segments, in a mutually exclusive way, by the units connected to each of the segments and by the buffers for concatenation of each of the segments with at least one adjacent segment.

Computer system with a bus having a segmented structure

In a multiprocessor system with shared resources, which several processors access via a system bus by presenting bus access requests to an arbitration unit and receiving from the latter access grant signals and in which the busy state of a resource or a conflict of consistency determine the generation of a RETRY signal and compel the processor, which has obtained access to the bus, to execute an access RETRY attempt, consecutive repeated access RETRY attempts of the same processor activate logic of the arbitration unit which temporarily mask, for a varying duration, the access requests of the same processor for the execution of further consecutive RETRY attempts, the varying duration first increasing as a function of the number of further RETRY attempts and then varying in a random manner.

Unit for arbitration of access to a bus of a multiprocessor system with

A memory access limiter for random access dynamic memory of data processing systems formed by several modules which can be independently activated in partial temporal superimposition, each by a memory start command, comprising a bidirectional counter which periodically increments at a constant period defined by a clock signal, by a value representative of the electrical charge delivered by a power supply to an output buffer capacitor and decrements, at each memory start command, by a value representative of the electrical charge drained at each memory operation activated by the memory start command, a predetermined decremented count state of the counter identifying a maximum admissible discharge condition of the buffer capacitor below which it is necessary to inhibit any further activation of the memory until the count state of the counter is no longer below the predetermined count state.

Memory access limiter for random access dynamic memories

In a synchronous arbitration unit with round-robin priority for arbitrating between N requests (Ri) for access to common resources of a multiprocessor system, the requests stored in an input register timed by a clock signal are applied as inputs to a fixed-priority arbitration network having 2N-1 inputs, N-1 of the requests being applied both to a first set of N-1 lower-priority inputs of the network and, through masking circuits which selectively mask the requests with a binary masking configuration generated by mask-generating circuits in accordance with predetermined priority-rotation criteria, to a second set of N-1 higher-priority inputs of the network, in the same order of input priority. The grant signals output by the network are latched in an output register after logical OR of the grant signals associated with the same request and the arbitration unit thus formed has a minimal arbitration time and is constituted by a small number of logic components.

Arbitraion unit with round-robin priority, particularly for

A multi-processor system in wherein a plurality of processors have access to a plurality of shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control unit and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory control unit, whilst the transfer of data to and from the memory modules takes place through data channels which connect the various processors on a point-to-point basis to the interconnection logic circuits and via these to a memory data transfer channel.

Multi-processor system with shared memory

Resolution transforming raster based imaging system where an image is formed by displaying dots arranged along scan lines, scanned by an energization beam, the scan lines having a predetermined resolution and the system is driven by an image bit map having rows with resolution multiple of said predetermined resolution, a subset of the rows being related to the scan lines, bits in rows unrelated to scan lines, and representative of dots to the displayed being displayed as dots offset to a next adjacent scan line and with a size related to the surrounding bit pattern.

Resolution transforming raster based imaging system and related

A method and associated apparatus for enhancing the display or print of greys in a two-tone digitized image consisting of storing a portion of a binary image map including a central bit under examination to be displayed and in testing if the said central bit is representative of an isolated dot or whether in a region around the said central bit in one of a plurality of predetermined directions there is an isolated dot at a predetermined distance from the said central bit, to display the central bit as a dot of reduced dimensions in such a way as to convert the display of an isolated dot in the display into a plurality of smaller dots with aggregate areas equivalent to the isolated dot and distributed around the location of the isolated dot identified from the image map.

Method and apparatus for improving the display of greys in a two-tone

Apparatus for the detection and correction of digitized image defects comprising a plurality of registers for storing a plurality of bits representative of a portion of digitized image comprising a central pixel and pixels surrounding the central one, means for reading out from said registers, through a sequence of reading operations, the level of the bits representative of said central pixel and of the pixels in the same row and column of said central pixel with a first read operation and the level of the bits representative of rows and columns of pixels adjacent to the central pixel and more and more far therefrom at each subsequent read operation, four sequencers receiving said bit levels and respectively analyzing a sector of the image portion located left, right, above and below the central pixel, the sequencers providing signals as result of such analysis to a decoder which outputs correction codes dependent on such analysis to a control unit of a visualization unit.

Apparatus for realtime detection of digitalized image defects and their

Electrophotographic printing apparatus with enhanced printed image capability in which the image is formed by dots located at image pixels having a predetermined size, comprising a scanning light beam source and circuits for modulating the light beam so as to form dots having a size in the direction transverse the scan direction equal, smaller or greater than the pixel size.

Electrophotographic printing apparatus with enhanced printed image

Cache memory having pseudo virtual addressing, in which the addressing is performed by using the 'offset' field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

Cache memory having pseudo virtual addressing

Timing unit for generating a timing signal for synchronous microprocessors in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor. A frequency divider divides the base frequency by four, and a shift register clocked by the base frequency and receiving a timing signal from the frequency divider, generates a mask signal. The mask signal is selectively applied to a control input of the frequency divider in response to one or more control signals, to inhibit the switching of the frequency divider. This thereby introduces in the phases of the timing frequency, wait states equal to 1/4 (or multiple thereof) of the timing frequency, thereby matching the microprocessor speed to the memory read/write cycle time.

TTL technology digital timing unit

A multiprocessor computing system includes a plurality of processors which are connected to each other through a system bus. Each processor comprises a processing unit, a local memory and an interface unit, which are interconnected so that the processing unit of any processor has access to both its own local memory and the local memory of any other processor through such interface unit and the system bus for concurrently writing into all of the local memories, information identified by a destination code as a global data.

Multiprocessor system featuring global data multiplation

Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a section with a plurality of bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces an information output code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code, and further bits indicative of a corrected single error and a multiple error which cannot be corrected.

Memory systems and related error detection and correction apparatus

An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer. The microinstruction transfer speed from working memory to the processor is further enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. In the case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register is loaded. In the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two overlap.

Asynchronous bus multiprocessor system

Apparatus for carrying out a set of macroinstructions by means of a microprogram in firmware. The apparatus controls the operating system of a digital computer which is adapted to carry out a set of macroinstructions. The macronistructions are carried out by means of a microprogram in firmware having a fetching phase and an execution phase. Both fetching and execution of macroinstructions are carried out by means of microprograms. One ROM is provided for storing a fetching and execution digital-word, associated with a macroinstruction and contains information relative to each phase respectively. Another ROM is provided for storing the actual microprograms for fetching and executing macroinstructions respectively.

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Cornaredo, Italy

Ferruccio Zulian