Unisys Corporation

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Gary J Lucas

Glen R Kregness

Kenichi Tsuchiva

A method and apparatus for granting exclusive access to a selected portion of addressable memory to a requesting processor in a large scale multiprocessor system. An instruction processor having a store-through operand cache executes an instruction requiring exclusive access to an address in a shared memory. If the address upon which the lock is requested is not in the local cache, the instruction processor simultaneously sends a lock and read request to the coupled storage controller. Otherwise, a no-operand-read and lock request is sent to the storage controller. If, while processing the lock request, no conflict is detected by the storage controller, the address is marked as locked and a lock granted signal is issued to the requesting processor. Concurrent with the processing the lock request the storage controller processes the read request. The lock granted signal and requested data are returned to the requesting processor asynchronously. The requesting processor can continue processing the lock instruction when the lock granted and required data have been returned from the storage controller. When two or more processors contend for a lock on a the same portion of addressable memory, one processor is granted the lock while the other contending processor(s) are forced to wait. Lock contention is arbitrated by a round robin priority scheme.

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Mayer, MN, United States of America

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