Unisys Corporation

Ferris T Price, Deceased

Larry L Byers

Eugene A Rodi

Donald W Mackenthun

Kelvin S Vartti

Gregory B Wiedenman

James F Torgerson

Thomas T Kubista

Gerald J Maciona

Dale K Seppa

Marvin W Theis

Jeff A Engel

Philip J Fye

An outboard file cache extended processing complex for use with a host data processing system for providing closely coupled file caching capability is described. Data movers at the host provide the hardware interface to the outboard file cache, provide the formatting of file data and commands, and control the reading and writing of data from the extended processing complex. Host interface adapters receive file access commands sent from the data movers and provide cache access control. Directly coupled fiber optic links couple each of the data movers to the associated one of the host interface adapters and from the nonvolatile memory. A nonvolatile memory to store redundant copies of the cached file data is described. A system interface including bidirectional bus structures and index processors that control the routing of data signals, provides control of storage and retrieval of file cache data derived from host interface adapters and from the nonvolatile memory. Multiple power domains are described together with independent clock distribution within each power domain. The independent clock distribution sources are synchronized with each other. A system for fault tolerant redundant storage of file cache data redundantly in at least two portions of the nonvolatile file cache storage is described.

Fault tolerant extended processing complex for redundant nonvolatile

The disclosure relates to a high performance fault tolerant queuing system. Multiple processors share access to one or more queues which are stored in an addressable memory. A storage controller provides general access to the addressable memory and includes queue functions for maintaining the queues. Queue access is provided in a first-come/first-served basis. In addition to the get and put queue functions, queue control within the storage control saves a queue item which is read from the queue in a location in the addressable memory which is associated with the processor making a get request, thereby alleviating the requesting processor from having to save the queue item.

Fault tolerant apparatus and method for maintaining one or more queues

A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coincides with every Nth clock cycle. This is important in various types of computers systems including high reliability systems because it results in a clock switching circuit which can provide a clock signal which remains consistent throughout the computer system even in light of multiple hardware failures.

Glitch free clock start/stop control circuit for outputting a single

A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.

Architecture for smart control of bi-directional transfer of data

A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.

VLSI embedded RAM test

A memory system providing capability for correction of multiple bit errors. The storage elements of the memory system are divided into four-bit nibbles, wherein storage of a single 32-word requires access to eight separate storage elements. A ninth storage element stores a four-bit error syndrome. All nine storage elements have single bit error correction/multiple bit error detection. All single bit errors are corrected directly within the individual storage element. Multiple bit errors within a single storage element are signaled to the interface controller which corrects the error using the stored four-bit error syndrome.

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Mayer, MN, United States of America

Ferris T Price, Deceased