International Business Machines Corporation

Fernando Quintana

Sushama M Paranjape

Steven Ross Bentley

Stephen C West

Michael Philip McIntosh

Charles Anthony Thompson, Jr

Charles E Bailey

Leonard George Jesionowski

Brian Gerard Goodman

Raymond Yardy

Frank David Gallo

Anthony Andrew Lambert

Kristy Colleen Judd

Rickey W Murray

Michael Pillip McIntosh

A power limiting system and method are provided for limiting power delivered to a common bus in a one or multi-frame tape library environment. The system includes one or more frames coupled to a common bus, each of which is capable of delivering power to the common bus. Each frame comprises current limiting circuitry to limit the power delivered by that frame to the common bus. In exemplary embodiments, the current limiting circuitry of each frame includes a current limiting resistor and a blocking diode coupled to a local power source to limit the power delivered by that frame and to prevent feedback respectively. Additionally, each frame of the system includes a relay capable of receiving a limited power from the common bus, being energized, and, consequently, providing for the respective frame to be powered by a main power supply. In exemplary embodiments, each frame includes a switch for taking power from the common bus to power a frame only when a respective local power source is on and a respective frame is energized. The method provided includes a method for coupling additional frames to a power limited common bus by limiting the power delivered by each frame. Specifically, the method provides for only those frames, which are delivering power to the common bus, to be powered by the power available on the common bus.

Power limiting system and method in a multiple power source environment

A distributed control system is provided for an automated data storage library. The library accesses data storage media in response to received commands, and comprises an accessor having a gripper for accessing the data storage media, and an XY system having servo motors for moving the accessor and the gripper. The distributed control system comprises a communication processor node for receiving commands, providing a communication link for the commands. An accessor processor node, which may be located at the accessor, is coupled to the communication processor node, the accessor processor node responsive to the linked commands, operating the gripper and providing move commands. An XY processor node may be provided at the XY system, coupled to the accessor processor node, the XY processor node responsive to the move commands, operating the servo motors. A common bus couples the communication processor node to the accessor processor node, and couples the accessor processor node to the XY processor node. A plurality of accessors may be provided, each with an accessor processor node coupled to the communication processor node.

Automated data storage library distributed control system

A method and apparatus is disclosed for maintaining states of an operator interface, such as an operator panel and convenience input/output station, of a dual library manager/dual controller system in the event of a failure to one controller during an operation. The invention allows control of the operator panel and convenience input/output station status lights and the states themselves by more than one controller without reinitializing at a default condition by detecting a failure during an operation, switching control to a second accessor controller and establishing a correct state for the operator interface via the second accessor controller. A correct state for a station is established by first establishing a fake empty status for the station and then locking the station, if necessary.

Method and apparatus for maintaining states of an operator panel and

An error tolerant detection of multibit synchronization characters within data blocks in a data storage system. Each detected prospective multibit synchronization character is compared to an expected multibit synchronization character for an identical match and for a match which includes a variation of no greater than two adjacent bits. A synchronization character is then considered to be identified in response to a successful exact comparison or, if relaxed detection is enabled, in response to a successful comparison indicating that the detected prospective multibit synchronization character does not differ from the expected multibit synchronization character by an error greater than two adjacent bits. For Read While Write operation in which it is imperative that the synchronization characters be written initially without error, the relaxed detection scheme may be selectively disabled, requiring the synchronization characters to achieve an exact match with the expected synchronization character.

Method and system for error tolerant synchronization character detection

A method and apparatus which first calculates track to track skew in a tape device and then uses the results of that calculation to adjust the windows for detection of sync and resync characters. The system makes use of global circuitry which adjusts the sync and resync windows for all tracks based upon the skew calculation. In the case of the windows used for detecting resyncs, when skew is determined to be large, the global resync window must span a larger time period to account for the skew in detecting resync marks. Conversely, when there is little or no skew present, the windows for resync detection can be narrowed. Normally, the track logic utilizes its own local windows to detect resyncs. If a track misses a resync, however, it must use the global resync window to determine the next resync location. Once the tracks are resynchronized, control can return to local track circuitry to maintain synchronization. In the case of force windows used for detecting the syncs after a resync alignment burst, the skew calculation is used to determine the correct sync location for each particular track. Further, data alignment is maintained in the multitrack environment through the use of a deinterleaving circuit which receives misalignment indications and, in response, makes address corrections to data bytes and pointer bytes.

Synchronizing data tracks using global force windows and track sync

An apparatus and method for detecting and validating formatted blocks during read/write data operations in a magnetic tape data storage system includes component functionality for reading and writing data on a magnetic tape medium in a plurality of modes, including a read-only (R) mode and a read-while-write (RWW) mode, the data being arranged in one or more tracks in a sequence of formatted blocks. In preferred embodiments, formatted block detection and validation is performed by appropriate logic circuitry configured to detect at least one formatting entity representing an inter-block gap, a block acquisition burst, a synchronization character, or any other desired formatting entity, using first and second programmable detection thresholds that are the same or substantially the same in both the R and RWW modes. In addition, a validation determination is made in the RWW mode whether detection of the formatting entity satisfies an RWW error threshold that is greater than either of the first and second programmable detection thresholds. If the RWW error threshold is not satisfied, a message is generated indicating that a write retry may be required. In this way, the detection of various formatting entities is achieved uniformly during the R and RWW modes but provision is also made for applying a more stringent threshold criteria during the RWW mode for write validation.

Apparatus and method for detecting and validating formatted blocks on

A method and system for locating and predicting synchronization characters within data blocks stored within multiple tracks on a removable data storage medium in a data storage system. The location and identity of each diverse synchronization character within multiple data blocks is predicted in response to an identification of an initial acquisition character and an identification of a particular data storage format. A first synchronization character is predicted and a synchronization counter is then incremented in response to a detection of each subsequent synchronization character, or, in response to the elapse of one of two predetermined delay periods. A system clock delay period is initiated immediately after each synchronization character is detected and the synchronization counter is then incremented at the end of that delay period. A second delay period is initiated thereafter, utilizing a derived track clock signal, which is reasonably insensitive to variations in storage media transport speed. The expiration of this second delay period is then utilized to increment the synchronization counter, if no synchronization character has been detected prior to that occurrence. In this manner, variations in tape speed and an occasional missed synchronization character may be accommodated and the identity and location of predicted synchronization characters may be accurately determined.

Method and system for synchronization character location and prediction

A method and system for accurately reading and storing data as multiple data blocks on a removable data storage medium mounted within a data storage system. Each data block includes an initial acquisition data character and multiple diverse synchronization characters/bursts and adjacent data blocks are separated by a unique interblock gap character. A multimodal interblock gap character detection circuit is provided which may operate in a normal mode of operation or a stringent mode of operation, wherein an enhanced degree of certainty is required for detection of the interblock gap character. A predicted time window of occurrence for a next interblock gap character is generated in response to detection of an initial acquisition data character and at least one synchronization character within a data block. Additionally, a global clock count signal based upon multiple track outputs is generated each time a resynchronization burst is encountered. The multimodal interblock gap character detection circuit is then automatically switched from the stringent mode of operation to the normal mode of operation during the predicted time window, minimizing the possibility of erroneous interblock gap character detection during data block processing. In data blocks which are sufficiently large to utilize multiple unique end of block synchronization characters, the occurrence of each successive end of block synchronization character may be utilized to redefine the predicted time window with greater accuracy. Expiration of a predicted time window or the occurrence of a global clock count signal during an open predicted time window may then be utilized to generate a presumption of the occurrence of an interblock gap character; however, actual detection of the interblock gap character will override the prediction circuitry.

Data storage system having multimodal interblock gap detection utilizing

A method and apparatus which first calculates track to track skew in a tape device and then uses the results of that calculation to adjust the windows for detection of sync and resync characters. The system makes use of global circuitry which adjusts the sync and resync windows for all tracks based upon the skew calculation. In the case of the windows used for detecting resyncs, when skew is determined to be large, the global resync window must span a larger time period to account for the skew in detecting resync marks. Conversely, when there is little or no skew present, the windows for resync detection can be narrowed. Normally, the track logic utilizes its own local windows to detect resyncs. If a track misses a resync, however, it must use the global resync window to determined the next resync location. Once the tracks are resynchronized, control can return to local track circuitry to maintain synchronization. In the case of force windows used for detecting the syncs after a resync alignment burst, the skew calculation is used to determine the correct sync location for each particular track. Further, data alignment is maintained in the multitrack environment through the use of a deinterleaving circuit which receives misalignment indications and, in response, makes address corrections to data bytes and pointer bytes.

Growing community of inventors

Tucson, AZ, United States of America

Fernando Quintana