Micron Technology Incorporated

Fernando Gonzales

Klaus Florian Schuegraf

Aftab A Ahmad

Nanseng Jeng

Mike P Violette

A semiconductor structure pad oxide layer is enlarged by local oxidation of silicon to form a field oxide. An etchback causes the thinnest portions of the field oxide to recede such that a portion of the semiconductor substrate is exposed. An etch through the exposed portion of the semiconductor substrate forms a microtrench between the field oxide and the nitride layer with a lateral dimension that is less than that currently achievable by conventional photolithography. The microtrench is then filled by oxide or nitride growth or by deposition of a dielectric material. In another embodiment, formation of the microtrench is carried out as set forth above, but the nitride layer is removed immediately following trench formation. Alternatively, the pad oxide layer is stripped and a new oxide layer is regrown that substantially covers all exposed surfaces of active areas of the semiconductor substrate. The regrown oxide layer will encroach into all exposed surfaces of active areas and will grow also in the microtrench. Alternatively, the pad oxide layer is etched substantially uniformly at regions distant from nitride layer, whereas the etchant concentrates the etch against the nitride layer such that etching is accelerated at this location. Because of accelerated etching at this location, a breach in the pad oxide layer forms before etching of the pad oxide layer has been generally penetrated. The breach has a width of sub-photolithographic limits preparatory to formation of a microtrench thereunder.

Isolation structure having trench structures formed on both side of a locos

Method of forming a LOCOS trench isolation structure

This invention is a DRAM array having stacked-capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a 5-mask process for fabricating such an array. The array has a cross-point cell layout (i.e., a memory cell is located at each intersection of each digit line and each word line) and tungsten digit lines formed using a damascene process buried in the substrate. Each cell in the array has a vertical transistor, with the source/drain regions and channel region of the transistor being formed from epitaxially grown single crystal silicon. The stacked capacitor is fabricated on top of the vertical transistor.

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Boise, ID, United States of America

Fernando Gonzales