Marvell International Limited

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Inphi Corporation

Fernando De Bernardinis

Rinaldo Castello

Luca Vercesi

Brian Taylor Brunn

Gregory Takeo Uehara

Alessandro Venca

Jody Greenberg

Chao Yang

Ruoxin Jiang

Antonio Liscidini

Marc Leroux

Davide Visani

Luca Fanori

Carlo Tinella

Danilo Manstretta

Marck Leroux

Clock data recovery circuitry, for a deserializer of a data transceiver, includes a clock recovery loop with a first feed-forward equalizer having a smaller number of taps and operating on received signals to recover a clock signal, and a data recovery loop including a second feed-forward equalizer having a larger number of taps, operating on received signals to recover a data signal. Output of the second feed-forward equalizer is coupled to output of the first feed-forward equalizer to improve recovery of the clock signal. The clock recovery loop may include adaptation circuitry configured to operate on output of the first feed-forward equalizer to counteract effects, on the clock signal, of adaptation of the second feed-forward equalizer by signals output by a decision feedback equalizer in the data recovery loop.

Clock path equalization in dual path CDR

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

Dual loop for clock recovery in CDR

A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.

Baud-rate time error detector

Embodiments described herein provide an electronic device, which includes a first oscillator configured to output a first clock signal, and a second oscillator that is co-located with the first oscillator on the electronic device. The electronic device further includes a first bandpass filter configured to filter a first input signal derived from the first clock signal received through a negative feedback loop, and to output a first signal component corresponding to the first signal spur. The electronic device further includes a signal reconstruction circuit configured to receive the first signal component and to combine the first signal component into a control signal for the first oscillator, and to feed the control signal combined with the first signal component to the first oscillator to mitigate the first signal spur exhibited in the first clock signal.

Systems and methods for suppressing oscillator-induced spurs in frequency synthesizers

Embodiments described herein include methods and systems for measuring channel impulse responses in a digital communication system. Specifically, statistical properties of the received signals at the receiver of the digital communication system are analyzed to compute, in real time, channel coefficients indicative of the channel state information, which may be time-dependent, without the use of a training signal.

Systems and methods for measuring impulse responses in a digital communication system

In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Transmit architecture for wireless multi-mode applications

A calibration circuit for calibrating harmonics in a mixer. The calibration circuit includes an RF signal path configured to receive an RF signal corresponding to an output of the mixer, selectively receive a test signal injected into the RF signal path, and provide feedback to the mixer according to the RF signal and/or the test signal. The test signal corresponds to a selected harmonic of the harmonics in the mixer. A measurement circuit is configured to detect, in the output of the mixer, the test signal injected into the RF signal path. A calibration module is configured to receive a feedback signal indicative of the test signal detected in the output of the mixer and, based on the feedback signal indicative of the test signal detected in the output of the mixer, adjust a duty cycle associated with the mixer to calibrate the selected harmonic.

Calibration circuit and methods for calibrating harmonics in a mixer

A clock and data recovery (CDR) apparatus includes an analog to digital converter configured to sample an input signal according to a sampling clock and provide a digitized signal, a first loop circuit configured to provide a first equalized signal corresponding to the digitized signal, and a slicer configured to provide a data signal based on the first equalized signal. A second loop circuit is configured to provide a second equalized signal corresponding to the digitized signal and adjust the sampling clock according to the second equalized signal. A CDR method includes converting an analog signal into a digitized signal using a sampling clock, providing a first equalized signal using the digitized signal, providing a second equalized signal using the digitized signal, determining the sampling clock using the second equalized signal, and generating a data signal using the first equalized signal.

Dual loop clock and data recovery

An apparatus comprises a plurality of Analog to Digital Converter circuits (ADCs) and a skew detector configured to determine a plurality of indicators corresponding to a plurality of sampling time skews of the plurality of ADCs, respectively. The plurality of ADCs is configured to adjust the plurality of sampling time skews according to the plurality of indicators, respectively. The apparatus is configured to reach an equilibrium state wherein the plurality of indicators are substantially equal. In an embodiment, the apparatus comprises a Time-Interleaved ADC including the plurality of ADCs. A method comprises measuring a plurality of indicators of a plurality of sampling time skews, respectively. The plurality of sampling time skews are associated with a plurality of ADCs, respectively. The plurality of sampling time skews are adjusted according to respective indicators of the plurality of indicators.

Methods for sampling time skew compensation in time-interleaved analog to digital converters

Embodiments of the present disclosure provide system and method for generating a transmission signal. A transmitter generates and transmits a transmission signal based on signal components. Circuitry that is coupled to the transmitter receives complex plane components of a signal to be transmitted and alters the signal such that a complex plane trajectory of the signal passes nearer to an origin of a complex plane of the complex plane trajectory than does an original complex plane trajectory of the signal. The circuitry determines the signal components to be transmitted by the transmitter based on the altered signal.

Avoiding frequency spikes in modulated systems

A system includes a radio frequency (RF) signal path configured to receive an input signal that includes at least one of a test signal and an RF signal. A local oscillator (LO) signal path is configured to supply a LO signal. A mixer includes a first input in communication with the RF signal path and a second input in communication with the LO signal path. A calibration control module is configured to receive an output of the mixer in response to the test signal and to adjust an effective duty cycle of the LO signal in the LO signal path based on the output of the mixer.

Systems and methods for calibrating harmonic rejection in switching mixers

An apparatus increases the dynamic range of a time to digital converter. The apparatus includes: an input network configured to receive a first signal, a second signal, and a control signal having a sign value; and a time-to-digital converter (TDC) configured to generate a digital code value that represents a time delay value between the first signal and the second signal. The input network is configured to switch where the first signal and second signal are output in response to the sign value that is determined by the time delay value between the first signal and the second signal.

Apparatus for doubling the dynamic range of a time to digital converter

In one embodiment, an apparatus includes a first circuit of a digitally controlled oscillator (DCO). The first circuit has a loss component. A second circuit is coupled to the first circuit and configured to transform a positive impedance into a negative impedance in series with a negative resistance. The negative impedance includes an adjustable reactive component used to adjust a frequency of an output signal of the DCO. An equivalent reactance seen by the first circuit is less than a reactance of the adjustable reactive component.

Tuning circuit for inductor capacitor (LC) tank digitally controlled oscillator

Aspects of the disclosure can provide a second order low pass filter. The second order low pass filter can work in current domain, and have high linearity for in-band signals and out-of-band signals. The second order low pass filter can include a MOS transistor having a gate terminal, a current input terminal and a current output terminal, a first capacitor coupled between the current input terminal and a ground connection and a second capacitor coupled between the gate terminal and the current input terminal.

Growing community of inventors

Pavia, Italy

Fernando De Bernardinis