Texas Instruments Corporation

Fernando D Carvajal

Mark William Morgan

David D Briggs

Charvaka Duvvury

Steven J Tinsley

Baoson Nguyen

Kambiz Hayat-Dawoodi

Anil Kv Kumar

Yanli Fan

Joe R Trogolo

Roy Clifton Jones, Iii

Thomas A Schmidt

Stephen C Kwan

Frank L Thiel

Todd M Neale

Srikanth Gondi

Chao-Chih Chiu

Kevin J Gingerich

An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting an output signal for the receiving device; each respective at least one output locus presents an output signal in response to the input signal received at a respective input locus of the at least one input locus; (b) a feed forward circuit coupling each respective input locus with its respective corresponding output locus to provide a feed forward signal to the respective corresponding output locus; the feed forward signal is in phase with the input signal received at the respective input locus.

Apparatus and method for handling interdevice signaling

System and methods are provided for monitoring circuit performance and correcting for variations in current reference signals to maintain a desired Voltage Output Differential (VOD) between the two differential output signals. A voltage signal associated with VOD is compared to a signal that is set to a desired voltage level based on a desired VOD. By determining whether the VOD level is higher or lower than the desired level, adjustments are made to at least one of an output current source level and an output current sink level. An increase in the source and sink currents at the output results in an increased VOD, while a balance decrease in the source and sink currents results in a decreased VOD.

Voltage output differential (VOD) correction circuit for differential drivers

Transitions (e.g. high to low and/or low to high) associated with operation of the driver are employed to implement control, which can be applied as a pulse in response to an occurrence of the transition. The control operates to speed up the transition at the output of the driver, such as can reduce driver switching times and enable a corresponding increase in data transmission rates.

System and method to speed-up operation of a driver

A method for isolatively coupling an input signal to an output signal, where the input signal is a first voltage differential, comprises three steps. Step one calls for generating a magnetic field that is indicative of the input signal in at least one magnetic sensor in an integrated circuit by generating a current through a conductor in the integrated circuit. The current is generated by applying the first voltage differential across the conductor, which is proximate the magnetic sensor. Step two requires generating a second voltage differential between two points of the magnetic sensor by providing a current through the magnetic sensor in a direction having a component transverse to the magnetic field. Step three calls for providing a signal indicative of the second voltage differential as the output signal, thereby isolatively coupling the input signal to the output signal.

Method and system for isolated coupling

A differential line driver with 4X supply voltage swing with a 1:1 transformer, which enhances the loop length for applications such as digital subscriber line includes: a differential circuit having first and second input nodes, first and second output nodes and and a supply voltage node; a transformer having a first coil coupled between the first and second output nodes; and a center tap of the first coil coupled to the supply voltage node. The device also acts as an active impedance termination, which eliminates the series termination resistor in conventional hybrids and thereby saving 6 dB transmit power.

Power efficient line driver with 4X supply voltage swing and active termination

A low voltage 485-driver circuit that meets the standard leakage and 1.5 voltage differential output requirements of the TIA/EIA-485 specification while operating from a 3V supply. The circuit avoids the voltage drop across the series Schottky diodes in the output driver of a conventional 485-driver by moving the Schottky blocking diodes from the output stage signal path to the pre-driver stage so that the output stage is restricted to back-gate biasing only. In addition, the circuit uses stacked NMOS transistors to maintain lower voltage across each NMOS transistor in order to prevent hot-carrier injection. This allows lower voltage rated output NMOS transistors to be used, resulting in higher speed operation. The circuit will withstand excessive common mode voltages in the range of &plus;12V to &minus;7V applied to the output while in either signaling ON state or the disabled OFF state.

Three-volt TIA/EIA-485 driver circuit

A fast voltage differential signaling (LVDS) transceiver ( ) having high repeater speeds up to 1.36 GBps, and also meeting the TIA/EIA-644 standard short-to-ground requirements. A mixed voltage-current mode differential driver has a respective control signal (A ) driving each of the drive transistors (Q ). The control signal (A ) is controlled by a transistor (M ) being a function of current through the respective drive transistor (Q ). A current mirror (Q , Q , Q ) is used to mirror current conducting through a transistor (Q ) in parallel with the drive transistor (Q ), which mirror current is compared against a current reference (Iref).

Voltage/current mode TIA/EIA-644 compliant fast LVDS driver with output current limit

An active fail-safe method and apparatus for a LVDS receiver that uses a window comparator circuit to monitor the differential voltage at the receiver's input pins and drive the output to a known logic HIGH state in the absence of a valid input signal; i.e., when the input differential signal is less than a chosen threshold value of approximately 80 mV. Such a condition may occur when the cable is removed or damaged in such a way that no valid input signal is present. In the presence of a valid input signal, the circuit's output tracks the differential input without any degradation to the signal.

Methods and apparatus for a terminated fail-safe circuit

A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Low-current oscillator with hysteresis input buffer

A three-state CMOS output buffer (,), having protective circuitry and an output node (OUT) connected to a bus, prevents damage to a connected integrated circuit when the bus voltage exceeds a power supply reference voltage (V,). A final output stage of the output buffer (,) includes a first pull-up transistor (QP,), a clamping transistor (QN,), and a pull-down transistor (QN,). A half-pass circuit (QN,) blocks the output voltage from propagating through the final output stage to damage the output buffer (,) when the output voltage applied to the output node (OUT) exceeds the supply voltage. The protective circuitry uses a clamping circuit (,), a switching circuit (,) and a backgate bias circuit (,) to prevent a leakage path between the output node (OUT) and the power supply reference (V,) through the source/bulk junction of biased transistors in the output buffer (,). The clamping circuit (,) turns the pull-up transistor (QP,) fully off when the output buffer (,) is enabled and an input signal (V,) is high and when the output buffer (,) is disabled. When the output buffer (,) is disabled, the switching circuit (,) turns the clamping circuit (,) off prior to turning the half pass circuit (QN,) and the pull-up transistor (QP,) off. The backgate bias circuit (,) provides a bias voltage equivalent to the power supply reference voltage (V,), as long as the bus voltage is not higher than the power supply reference voltage (V,), and bias equivalent to the bus voltage, when the bus voltage exceeds the power supply reference voltage (V,). Thus, the protective circuitry provides protection without a glitch of bus voltage propagating through the final output stage.

Output buffer for a low voltage differential signaling receiver

A circuit (,) operates at relatively low values of the supply voltage, and includes a differential input circuit (,) which receives a differential input signal at first and second terminals (,). A differential voltage derived by the input circuit from the differential input signal is present at third and fourth terminals (,) and is amplified by a differential amplifier (,). A differential level adjuster (,) adjusts output voltages from the amplifier to suitable values for application to a matcher (,). The matcher (,) generates two currents that also flow within a differential compensator (,), and that match respective currents flowing in the amplifier. The differential compensator then provides a suitable current to each of the third and fourth terminals, such that the current flow between the first and third terminals, and between the second and fourth terminals, is substantially zero.

Low voltage amplification circuit with bias compensation

A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Efficient NPN turn-on in a high voltage DENMOS transistor for ESD

The invention is a multiplex circuit for outputing two or more signals of different levels to a common output pad where a first output driver (D.sub.h) is powered from a voltage rail having a higher voltage than at least one second output driver (D.sub.1) power by a lower voltage rail. An interface circuit (IFC) and level shift circuit provides two output signals base on a single input signal, one signal being equivalent to the voltage of the higher voltage (V.sub.High) and the other being based on the lower voltage (V.sub.low). PMOS device connected to the output pad has its back gate connected to V.sub.high to prevent leakage current through the PMOS device when the output to the output pad (P.sub.1) is equivalent to V.sub.High.

Multiplexing a single output node with multiple output circuits with

Method of making an efficient NPN turn-on in a high voltage DENMOS

A CMOS oscillator includes two differential input transistors (150) and (152) which have the sources thereof coupled through a resonator element (196). Active loads (166) and (178) provide a squaring up of the output which then drives an output transistor (202). The gates of the differential input transistors (150) and (152) are biased to predetermined voltage levels with bias circuits, with the positive input of the comparator configuration coupled through a feedback capacitor (208) to the output (204). This provides sufficient instability to initiate oscillation with a gain of the device controlled by resonator circuit (196) to be optoimum at the resonant frequency of the resonator circuit.

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McKinney, TX, United States of America

Fernando D Carvajal