Nxp USA, Inc.

Freescale Semiconductor,inc.

Fernando A Morales

Sanjay Raghunath Deshpande

Thang Q Nguyen

John E Larson

Mark Banse

A data processing system includes a plurality of processing unit. Each processing unit includes notification storage circuitry configured to store a notification indicator corresponding to each processing unit which indicates whether the processing unit has an outstanding coherent memory request, and multiple request storage circuitry configured to store a multiple request indicator corresponding to each processing unit which indicates whether the processing unit has more than one outstanding request. The data processing system also includes an interconnect network coupled between the processing units and configured to broadcast coherent memory requests from a requesting processing unit of the plurality of processing units to other processing units of the plurality of processing units.

Multiple request notification network for global ordering in a coherent mesh interconnect

Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

Methods and systems for controlling ordered write transactions to multiple devices using switch point networks

A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. Each processing unit which is not a root or leaf of the directed spanning tree includes switch point circuitry having one or more ingress ports coupled to neighboring processing units in accordance with the directed spanning tree. The switch point circuitry includes a coherency tracking table configured to store a combined coherency response in response to a particular snoop request based on one or more coherency responses received at the one or more ingress ports from the neighboring processing units.

Efficient coherency response mechanism

A network having a plurality of switch points, each switch point having both a main multi-stage pipeline and a look-ahead pipeline between input ports and output ports of the plurality of switch points is described. The look-ahead pipeline has fewer pipeline stages than the main multi-stage pipeline. Look-ahead information and corresponding packet are received at an input port. A first stage look-ahead request is generated from the look-ahead information. A second stage look-ahead request is generated in response to the first stage look-ahead request being not granted. And in response to the second stage look-ahead request being granted, transmitting a packet through the switch point using the look-ahead pipeline.

Switch point having look-ahead bypass

Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.

Piggy-back snoops for non-coherent memory transactions within distributed processing systems

A system and method for enhancing the security of containers and the goods within them and for tracking a shipping container from its origin to its destination. A shipping container uses a breach containment system comprising a transmitter, a receiver, a processor, a status record and a plurality of conductors to detect any breach of the shipping container structure. The conductors are embedded in, or applied to, the structures that form the shipping container and are connected a processor. The processor maintains a local timer. Upon the sealing of the shipping container, the conductors form circuits and the local timer contributes a time value to the status record. An open circuit condition experienced by circuits formed by the conductors causes the local timer to be reset and status record to be revised to reflect the revised time value. A monitoring station maintains a master timer that is synchronized with the local timer when the shipping container is sealed. If the integrity of the shipping container is breached, the local timer value and the master timer value will be different indicating that a breach has occurred. The present invention also provides for reporting of the content of the status record to reporting stations for forwarding to a monitoring station.

Growing community of inventors

Austin, TX, United States of America

Fernando A Morales