International Business Machines Corporation

Fernando A Luiz

John H Sorg, Jr

Gregory Michael Nordstrom

Martin W Sachs

Robert Bryan Cook

Salvatore A Calta

Harlan C Snyder

Henry Bardsley, Iii

Ronald C Simpson

Caryl A Thorn

Nils F Nilsen

Phillip R Mills

A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

Independent computer storage addressing in input/output transfers

Means are provided to prevent the failure of an Initial Program Load (IPL) command in a data processing system because of a 'busy' indication from a Direct Access Storage Device (DASD) control device which is executing the command. An IPL operation from a Central Processing Unit (CPU) involves the issuance of a System Reset signal to all channels and control units connected to the CPU, followed a short time later by a READ IPL command to the DASD control device controlling the DAS device which contains the program to be loaded. The present invention enables the system to distinguish between when a control device is busy with a System Reset procedure and when it is busy on other matters, and to permit the queueing of the READ IPL command when the control unit is busy and there is a System Reset operation pending so that the READ IPL command will not be rejected.

Preventing initial program load failures

A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means (FIG. 2, element 25') for storing a table of independent path sets of CPU's and reserved devices and means (FIGS. 2-5) for managing the connection of CPU's to devices such that for any given selection, reservation or reconnection indication, the table is accessed by at least one control node for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved, if so, an available path is selected. The control nodes thus allocate dynamically dissimilar path sets to devices and CPU's on an allegiance basis in order to increase the signal path connection probability by the devices to counterpart CPU's involved in the reservation, release, or reconnection of the device and the CPU.

Method and means for path independent device reservation and

A method and means for the recovery of non-logged data by a CPU/channel from a storage subsystem, which data would normally be overwritten upon the subsystem being RESET by the CPU/channels. A defaulting control unit simultaneously initiates a DISCONNECT IN sequence to its attaching channels and sets an appropriate status bit at a control unit/control unit communications interface. The channel responds to the DISCONNECT IN with a SELECTIVE RESET interface sequence which sequence is buffered by the defaulting control unit. Meanwhile, the companion functioning control unit, when operating at its lowest interrupt level, polls the status bit periodically and offloads data registers through the interface connection from the defaulting unit within a predetermined time. At the end of this interval, the SELECTIVE RESET is honored, thereby erasing all data in the defaulting control unit registers.

Method and means for CPU recovery of non-logged data from a storage

In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive requests from a high speed processor can give rise to an impasse condition in which the control unit is blocked from completing the previously initiated sequence between a peripheral device and another processor. In accordance with the invention, the interface between the processors and the peripheral devices incorporates means which detect an uninterrupted sequence, of predetermined length, of busy responses from the control unit. If such responses are not interrupted by other actions, the system temporarily exercises independent control, returning a busy signal to the processors while enabling the control unit to ascertain whether reconnection to a specific processor is needed as the next step in a previously initiated processor program. If so, the control unit is enabled within the predetermined interval to effect the reconnection, either within the allotted time or on a succeeding repetition of the cycle. The exercise of a limited initiative for a predetermined time interval does not alter the basic master-slave relationship or unduly delay data transfer operations.

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Monte Sereno, CA, United States of America

Fernando A Luiz