Cadence Design Systems, Inc.

Fernanda Augusta Braga

Georgia Penido Safe

Vincent Gregory Reynolds

Mirlaine Aparecida Crepalde

Yumi Monma

Felipe Althoff

Lucas Martins Chaves

Mariana Ferreira Marques

Pedro Bruno Neri Silva

The present disclosure relates to a method for electronic design verification. Embodiments may include identifying a plurality of higher level instances along an electronic design path from a source to a destination. Embodiments may further include analyzing inter-instance path information associated with the plurality of higher level instances included in the electronic design path from source to destination. Analyzing may include ignoring information included within the plurality of higher level instances. Embodiments may further include determining, based upon, at least in part, inter-instance path information whether data is unable to propagate from the source to the destination.

Applying a hierarchical proof to formal verification based path sensitization

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

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Castro Valley, CA, United States of America

Fernanda Augusta Braga