International Business Machines Corporation

Fernand J Dorleans

Geraldine C Schwartz

Gerald R Larsen

Louis L Hsu

John Anthony Fitzsimmons

Roy Arthur Carruthers

Paul J Tsang

Liang-Choo Hsia

James A Jubinsky

Robert W Zielinski

Richard Flitsch

Robert S Pokrzywa

Robert O Norton

The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted 'T'. A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

CMOS transistor with two-layer inverse-T tungsten gate

The present invention is directed to a unique method for fabricating a silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted 'T'. A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

Method for fabricating a MOS transistor with two-layer inverse-T

A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Structure and fabrication of SiCr microfuses

SiCr microfuses

A keying system for assuring the proper sequence or arrangement of cable cards within a card grouper is provided. The grouper includes a plurality of slots to receive the cable cards. The cards include tab means at at least one side thereof which can be selectively trimmed to one of several specific extension distances from the card. The grouper includes a template which has grooves configured to receive cards having their tabs programmed to one and only one configuration. Thus any given card, when programmed, will fit in only one location. The cards and grouper also include coacting surfaces to allow the appropriate card to be inserted in only one orientation in any given slot.

Keying system for assuring proper array configuration of cable cards

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Wappingers Falls, NY, United States of America

Fernand J Dorleans