Intel Corporation

Fern Nee Tan

Min Suet Lim

Eng Huat Goh

Alexander Levin

Srinivasan Rajagopalan

Tark Wooi Fong

Sanjiv Soman

Suk Yeak Lai

Jackson Chung Peng Kong

Khang Choong Yong

Jeff Ku

Tin Poay Chuah

Jiun Hann Sir

Ping Ping Ooi

Poh Tat Oh

Khai Ern See

Jenn Chuan Cheng

Jimmy Huat Since Huang

Siang Yeong Tan

Teong Keat Beh

Chu Aun Lim

Javed Shaikh

Deepak Sekar

Damien Weng Kong Chong

Tai Loong Wong

Kavitha Nagarajan

Thermal Management Systems for electronic devices and related methods are disclosed. An example electronic housing includes a housing defining a cavity, electronics in the cavity, and a touch display over the electronics. A heat spreader has a first surface toward the electronics and a second surface opposite the first surface toward the touch display, where the heat spreader is to dissipate heat generated by the electronics. A glass cover is coupled to the housing and has a first side toward the touch display and a second side opposite the first side, where the glass cover is exposed external to the housing. An insulation layer is between the second surface of the heat spreader and the second side of the glass cover to restrict heat transfer from the electronics to the second side of the glass cover.

Thermal management systems for electronic devices and related methods

The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.

Stacked scalable voltage regulator module for platform area miniaturization

Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops.

Capacitive interconnect in a semiconductor package

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.

Isolation module for use between power rails in an integrated circuit

Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

Apparatus utilizing computer on package construction

In one embodiment, the present invention includes an apparatus having core logic formed on a die, input/output (IO) buffers surrounding the core logic, and a moat capacitance surrounding the IO buffers and extending to an edge of the die. Other embodiments are described and claimed.

Providing a moat capacitance

A shielded test contactor to electrically couple a device to be tested to test circuitry, comprises conductive material covered by or embedded in non-conductive material and defining a well to receive the device. Contacts extend from the embedded conductive material to connect the embedded conductive material to ground. Preferably, the contacts are extensions of the conductive material, through the non-conductive material. A second non-conductive material is preferably provided to support the embedded conductive material and define a floor of the well. Electrical connectors are preferably also supported by the second non-conductive material adjacent to the well, to electrically couple the device to test circuitry. For example, the connectors may be pins supported by the second non-conductive material and extending into the well. Preferably, the height of the conductive material defining the well is at least twice the height of the device to be tested.

Grounded test contactor for electromagnetic shielding

Electromagnetically shielded test contactor

Growing community of inventors

Penang, Malaysia

Fern Nee Tan