Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Global Unlimited Company

Fergus John Downey

Dennis A Dempsey

Roderick McLachlan

Donal McAuliffe

Miguel Usach Merino

David A Browne

Peter Enright

Martina Mincica

Ivan Bucoy Santos

Thomas Murphy

Michael C Lynch

Ken Bryan Fulgosino Fabay

Christian Steffen Birk

Wes Vernon Lofamia

Fintan M Leamy

A configurable output stage for a DAC channel can include an output stage that can receive an analog output from a DAC and outputs a signal to an output terminal. The output stage can be configurable between a voltage mode and a current mode. In the voltage mode, the output stage can supply the analog signal to the output terminal as a voltage signal. In the current mode, the output stage can supply the analog signal to the output signal as a current signal. The output stage can receive user input to select the desired mode. Consequently, an integrated circuit can be implemented with multiple DAC channels, each having the configurable output stage. A user can choose how many channels they want to operate in a voltage output mode, and how many channels they want to operate in a current output mode, depending on their individual requirements.

DAC with configurable output stage

The present disclosure relates to an integrated circuit with at least a first channel and a second channel. Each channel includes at least a DAC. The integrated circuit also includes a number of circuit elements interconnected between the channels. The circuit elements can be changed between a short circuit state and an open circuit state. Normally, each channel will operate independently of one another, using only the circuit components in its respective channel. However, the circuit elements are arranged to allow a user to combine part of the second channel with the first channel to improve the functionality and performance of the first channel. In particular, a state of the circuit elements can be chosen to combine components of the second channel with the first channel. For example, components (e.g. a sub-stage) of the second channel can be connected in parallel with corresponding components (e.g. a corresponding sub-stage) of the first channel. This may reduce the number of available channels, since the second channel can no longer be used as an independent channel. However, the performance of the first channel is enhanced. The presence of the circuit elements allow an end user to decide whether to sacrifice channel count for performance enhancements. For example, the user can provide user input to the integrated circuit to select how the channels are interconnected. Moreover, the integrated circuit does not use additional redundant circuitry to improve the first channel, and rather takes components from the second channel. As such, the integrated circuit can have a reduced size.

Configurable DAC channels

A wearable sensor for measuring a parameter of human skin is described and includes a flexible body comprising sensor components formed on, adjacent or within the flexible body and configured to generate a first signal indicative of the parameter of human skin; microfabricated processing circuitry formed within the flexible body, coupled to the sensor components and configured to process the first signal to produce a second signal; and an antenna, formed on, adjacent or within the flexible body, the antenna being coupled to the processing circuitry and configured to transmit the second signal to an external device.

Wearable sensor and method of forming thereof

A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.

NMOS PTAT generator and voltage reference

A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the 'control' register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.

Multi-I/O serial peripheral interface for precision converters

Described are various techniques that can minimize the use of high-voltage devices in a unity-gain buffer that can be used in a high voltage application, while providing a circuit that generates an output that is an accurately buffered version of the input.

High-voltage unity-gain buffer

Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.

Current steering digital to analog converter

Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

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Oranmore, Ireland

Fergus John Downey