Stmicroelectronics S.r.l.

Stmicroelectronics (grenoble 2) Sas

Ferdinando Iucolano

Cristina Tringali

Santo Alessandro Smerzi

Romeo Letor

Alessandro Chini

Alfonso Patti

Maria Concetta Nicotra

Fabrizio Roccaforte

Giuseppe Greco

Andrea Severino

Paolo Badalá

Paolo Badala'

Antonio Filippo Massimo Pizzardi

Emanuela Schiliro'

Raffaella Lo Nigro

A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

Normally-off transistor with reduced on-state resistance and manufacturing method

An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

HEMT transistor including an improved gate region and related manufacturing process

An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

HEMT transistor including field plate regions and manufacturing process thereof

A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

Method for manufacturing a gate terminal of a HEMT device, and HEMT device

A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

Method for manufacturing an ohmic contact for a HEMT device

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Double-channel HEMT device and manufacturing method thereof

An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

HEMT transistor with adjusted gate-source distance, and manufacturing method thereof

A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method

An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

GAN-based, lateral-conduction, electronic device with improved metallic layers layout

An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

Method of manufacturing a HEMT device with reduced gate leakage current, and HEMT device

A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant ('lattice mismatch'), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof

A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

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Gravina di Catania, Italy

Ferdinando Iucolano