Cadence Design Systems, Inc.

Feras Al-Hawari

Jilin Tan

Dennis Nagle

Taranjit Singh Kukal

Raymond Komow

Ambrish Kant Varma

Jose Emmanuel Schutt-Aine

Ping Liu

Kumar Chidhambara Keshavan

Zhongyong Zhou

Qi Zhao

Roger Cleghorn

Shangli Wu

Yubao Meng

Terry Jernberg

A system and method are provided for maintaining alignment of timing signals of a source synchronous interface between driver and receiver portions of an electronic system in a behavioral model based simulation environment. The system comprises a memory unit, an analysis controller unit coupled to the memory unit, and a timing alignment unit coupled to the analysis controller unit. The timing alignment unit is executable responsive to the analysis controller unit to generate behavioral models for mutually assigned first and second nets which transmit respective timing signals between the driver and receiver portions, and actuates transient simulation on the behavioral models to simulate transmission of the timing signals through the first and second nets. A timing skew between respective transmissions of the timing signals through the first and second nets is measured responsive to the simulated transmission for compensation during a general simulation of the source synchronous interface.

System and method for automatic correction of flight time skew of timing signals in simulated source synchronous interface operation

The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.

System, method, and computer program product for input/output buffer modeling

A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

System and method for implementing power integrity topology adapted for parametrically integrated environment

A method and system are provided for parametrically adapting a behavioral model pre-configured for a preset supply reference level to fluctuations therein. The behavioral model is adaptively scaled for deviation of the electronic system supply reference from its preset level. The scaling includes reconstructing a surrogate device parametrically representative of a portion of the behavioral model's undisclosed circuit. The reconstruction includes pre-setting a transistor type for the surrogate device, such that the surrogate device is configured with a conductive channel current-voltage characteristic of the preselected transistor type. Device-specific properties for the surrogate device are generated based on selective cross-correlation of operating points between the conductive channel current-voltage characteristic and V-t and I-V curves associated with the behavioral model. An instantaneous value for a modeled current parameter may then be replaced with a scaled channel current value generated for the surrogate device responsive to supply reference deviation from its preset level.

System and method for adapting behavioral models to fluctuations in parametrically integrated environment

A method and system are provided for adaptively modeling and simulating high speed response of a transmission line. A simulation unit maintains a plurality of curve approximation options for modeling the transmission line. The suitability of a predefined primary one of the curve approximation options for modeling is determined based on frequency-domain modal scattering parameters obtained according to frequency-dependent data characterizing the transmission line. One of the options is selectively executed in response to the determination, in order to generate a macromodel of the transmission line. The primary option is executed upon determination of suitability, while a secondary one of the curve approximation options is alternatively executed upon determination of non-suitability. Transient simulation is then executed upon the resulting macromodel of the transmission line.

Method and system for adaptive modeling and simulation of lossy transmission lines

A system and method is provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

System and method for adapting electrical integrity analysis to parametrically integrated environment

A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

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Chelmsford, MA, United States of America

Feras Al-Hawari