Elbrus International Limited

Feodor A Gruzdov

Boris A Babaian

Yuli Kh Sakhin

Leonid N Nazarov

Sergey A Rozhkov

Mikhail L Chudakov

Valeri G Gorokhov

Vladimir V Tikhorsky

Vladimir Yu Volkonskiy

Vladimir Yu Volkonski

Vladimir Y Volkonsky

Vladimir V Rudometov

Alexey P Lizorkin

Vladimir S Volin

Valdimir Y Volkonsky

Alexander M Artymov

Evgeny Z Stolyarsky

A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.

Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution

Single-chip multiprocessor with cycle-precise program scheduling of parallel execution

A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Method for prioritizing operations within a pipelined microprocessor based upon required results

A method and system for preparing branch instruction of a computer program, for compiling and execution in a computer system, in which each transfer instruction is split into two instructions: a control transfer preparation instruction and a control transfer instruction, wherein the control transfer preparation instruction contains the transfer address and is placed by the compiler several instructions ahead of the control transfer instruction, so that the number of clock cycles in the pipeline between transfer condition generation and transfer itself would be reduced.

Branch preparation

A method and computer apparatus are presented for providing a secure data architecture for computer memory of a processor. The apparatus comprises a memory unit and a processing unit. Data are stored in the memory unit and manipulated by the processing unit, which is programmed to implement the data architecture. Tagged single data words are formed by concatenating a tag to each of the single data words. Each of the tags takes a value that corresponds to the data type of the single data word to which it is concatenated. A data multiword is creating by concatenating tagged single data words having the same data type. The data multiword is stored within a location in the computer memory, the location selected to ensure alignment of the data multiword in accordance with its length. An effective tag value is constructed for the data multiword by concatenating all of its single word tags. An operation is prevented from being performed on the data multiword if the effective tag value is not one of a predetermined list of valid effective tag values for the operation.

Integrity of tagged data

For certain classes of software pipelined loops, prologue and epilogue portions of adjacent inner loops in a nested loop can be overlapped. In this way, outer loop code, as well as inner loop code, can be software pipelined. Architectural support for software pipelined nested loops is provided by a set of loop parameter and status registers and by an implementation of loop state dependent, multiway control transfers. For loop body code compatible with two simple constraints, the present invention does not require additional code elements for disabling garbage operations during prologue and epilogue loop periods of adjacent inner loops. Nested loop control allows overlap between the epilogue period of a prior inner loop and the prologue period of a next inner loop. As a result, nested loop code can be more efficiently scheduled by a compiler for execution on a processor such as VLIW processor which provides architectural support for software pipelined nested loops, thereby providing improved loop performance. Loop state dependent, multiway control transfers are provided by multi-way control transfer logic which includes the loop parameter and status registers and a branch target selector for selecting control transfer addresses corresponding to inner loop body code, a start patch, and a finish patch from control transfer address registers in accordance with loop state.

Architectural support for software pipelining of nested loops

An array prefetch system improves processor performance by automatically tuning a statically compiled and compacted loop program at run-time to accommodate variations in latency of memory read operations. Using the array prefetch system, the processor, while awaiting completion of a data access, continues to generate requests for subsequent iterations rather than fully halting execution until a read access is finished.

Array prefetch apparatus and method

For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible with two simple constraints, code elements are not required for disabling garbage operations during prologue and epilogue loop periods. As a result, resources associated with implementation of the powerful architectural feature of predicated execution need not be squandered to service loop control. In particular, neither increased instruction width nor an increased number of instructions in the loop body is necessary to provide loop control in accordance with the present invention. Fewer service functions are required in the body of a loop. As a result, loop body code can be more efficiently scheduled by a compiler and, in some cases, fewer instructions will be required, resulting in improved loop performance. Loop control logic includes a loop control registers having an epilogue counter field, a shift register, a side-effects enabled flag, a current loop counter field, a loop mode flag, and side-effects manual control and loads manual control flags. Side-effects enabling logic and load enabling logic respectively issue a side-effects enabled predicate and a loads enabled predicate to respective subsets of execution units. Software pipelined simple and inner loops are supported.

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Moscow, Russia

Feodor A Gruzdov