Availink, Inc.

Fengwen Sun

Juntan Zhang

Ming Yang

Peng Gao

Zhiyong Wu

Jilong Li

Zhenliang Shi

Guofang Sheng

Yuhai Shi

Yingjiu Xu

Fangyi She

Yimin Jiang

A family of quasi cyclic irregular low density parity check codes for video broadcasting applications. The parity check matrices of the constructed low density parity check codes have quasi-cyclic structures to facilitate hardware implementation and have proper check/bit degree distributions to offer frame error rate performance lower than 10.

Family of LDPC codes for video broadcasting applications

A digital communications system and method to transmit and receive a digital communications signal wherein the digital signal has a plurality of frames, wherein at least two modulations are supported, and wherein each of the plurality of frames has the same number of symbols.

Efficient frame structure for digital satellite communication

A digital communication system, having a transmitter to transmit a digital signal; and a receiver to receive the digital signal; wherein the digital signal utilizes a 32APSK system with FEC coding, and the signal is bit-mapped using gray mapping, and bits of the digital signal are ordered based on the values of a log likelihood ratio from a communications channel.

Bit mapping scheme for an LDPC coded 32APSK system

An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Interleaving scheme for an LDPC coded 32 APSK system

An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Interleaving scheme for an LDPC coded QPSK/8PSK system

An approach is provided for interleaving low density parity check (LDPC) encoded bits in 16ASPK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.

Growing community of inventors

Germantown, MD, United States of America

Fengwen Sun