Apple Inc.

Fenghua Zheng

Sandro Hermann Pintz

Paolo Sacchetto

Christopher P Tann

David S Zalatimo

Marc Albrecht

David W Lum

Taesung Kim

Chaohao Wang

Howard H Tang

Jason N Gomez

Prasanna Nambi

Shatam Agarwal

James Aamold

Zhibing Ge

James E C Brown

Patrick B Bennett

Daibashish Gangopadhyay

Shih Chang Chang

Jun Qi

Hopil Bae

Chun-Yao Huang

Thomas James Wilson

Cheng-Ho Yu

ByoungSuk Kim

Szu-Hsien Lee

Kyung Wook Kim

Yi Huang

Hao-Lin Chiu

Xiaofeng Wang

Kwang Soon Park

Steven M Scardato

Johan L Piper

James E Brown

Yaser Azizi

Manev Luthra

Sachiko Oda

Jiaxi Hu

Joonggun Lee

Joseph P Manca

An electronic device may include a display having an array of pixels that receive data signals from multiple column driver integrated circuits. Each column driver integrated circuit may include gamma amplifiers that are used to set gamma references for driving the data signals. Each gamma reference can be set using first and second (redundant) gamma amplifiers in an alternating fashion to perform auto-zeroing. The auto-zeroing operation can be combined with a chopping operation to minimize amplifier offset across the different column driver integrated circuits. The auto-zeroing and/or the chopping function can be spatially alternated across the different rows in the array and temporally alternated across the different display frames.

Display column driver devices with offset cancellation

A system includes processing circuitry configured to determine a plurality of line-specific common voltage (Vcom) values for a plurality of common electrodes of an electronic display. Each of the plurality of line-specific Vcom values is associated with a line of pixels of a plurality of lines of pixels of the electronic display. Additionally, the processing circuitry is configured to cause the plurality of line-specific Vcom values to be provided to the plurality of lines of pixels.

Intra-frame interpolation based line-by-line tuning for electronic displays

Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.

Panel driver interface systems and methods for electronic device displays

Aspects of the subject technology relate to control circuitry for displays. A display control circuitry includes a plurality of amplifiers to drive gamma signals for a pixel array having a plurality of pixels of a display and a segmented resistor string coupled to the plurality of amplifiers. The resistor string includes a plurality of resistor segments with a resistor segment being designed with a modified resistance to modify display performance parameters including at least one of a settling time of an associated gamma signal, a power supply rejection ratio (PSRR) of an amplifier of the plurality of amplifiers, or an output voltage offset of an amplifier of the plurality of amplifiers.

Display circuitry and method to utilize segmented resistors for optimizing front of screen performance

An electronic device may include a display. The display includes display driver circuitry for driving data lines routed across the display. The electronic device may have a recessed device housing region, where at least some of the data lines are routed around the recessed region. The data lines being routed around the recessed region may be formed in at least two different metal routing layers. The electronic device may further include additional display driver circuitry for driving data lines from another peripheral housing edge to obviate the need to route around the recessed region. The data lines from the two display driver circuitries can be disconnected at random locations or can be interlaced to achieve spatial interleaving. The display driver circuitry may include demultiplexing circuitry having smaller switches coupled in parallel with larger demultiplexer routing switches to reduce voltage kick and charge injection.

Electronic devices with narrow border displays

An electronic device may include a display. The display may include display driver circuitry that is configured to provide image data to columns of pixels and gate driver circuitry that is configured to provide control signals to rows of pixels. The display may be operable at a native refresh rate that is equal to the highest refresh rate at which the display has full resolution. The display may also be operable in a high refresh rate mode with a high refresh rate that is twice (or some other scaling factor greater than) the native refresh rate. To enable operation at the high refresh rate mode, vertical resolution of the display may be sacrificed. In other words, rows of pixels may be grouped together into effective rows that are then scanned in sequence. The gate driver circuitry may be formed as thin-film transistor circuitry or from gate driver integrated circuits.

Displays with multiple refresh rate modes

The present disclosure relates generally to electronic devices, and more particularly, to electronic devices that utilize electromagnetic signals (e.g., radio frequency (RF) signals), transmitters, and receivers in various processes, such as cellular and wireless device processes in a at least partially metal enclosure. The present disclosure describes devices that may be used to wirelessly transmit and/or receive electromagnetic signals between processing components and sensing components, for example, by improving sensing device design and thus forming an integrated sensing tag that leverages passive RF technology, such as radio frequency identification (RFID) tags.

Integrated sensing tag-based wireless sensing within electronic devices

Aspects of the subject technology relate to electronic devices with displays. A display may include an array of display pixels and control circuitry for operating the display. The control circuitry may determine, based on pixel values for a row of display pixels, that a current in common supply voltage circuitry for the display pixels will exceed a threshold, if the row of display pixels is operated using the pixel values. The control circuitry may modify the pixel values for the row of display pixels to reduce the current in the common supply voltage circuitry and/or prevent the current in the common supply voltage circuitry from exceeding the threshold.

Current protection systems and methods for electronic device displays

Devices and methods for useful in providing localized synchronized and/or dynamic in-band internal gamma code adjustment per frame period are provided. By way of example, a display panel includes a data driver, which includes a first DAC configured to provide an internal gamma voltage signal to cause a first adjustment to an image data signal. The first adjustment is configured to selectively adjust the image data signal based at least in part on a refresh rate or a frame rate of the display panel. The data driver includes a second DAC coupled to the first DAC and configured to provide an external gamma voltage signal configured to provide a second adjustment to the image data signal, and an output buffer configured to supply the image data signal to pixels of the display panel, wherein the image data signal comprises the first adjustment and the second adjustment.

Internal gamma correction for electronic displays

The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Low power display device with variable refresh rates

This application relates to systems, methods, and apparatus for reducing the power consumption of a display panel. Specifically, the embodiments discussed herein relate to a panel pixel charge scheme that allows the current output of a display driver to be modified based on the content to be displayed at the display panel. The display driver can compare current and upcoming display content in order to determine how the line voltage for one or more output lines will change over time. If, based on the comparison, the voltage for an output line is not going to vary substantially over time, the bias current output from the display driver can be modified in order to save power. The modification to the bias current can depend on the amount of change the line voltage will undergo in subsequent executions of the content data.

Power efficient adaptive panel pixel charge scheme

Methods and systems for compensating for VCOM variations include determining a voltage change in pixels between frames to be displayed on an electronic display. Based on the determined voltage change, VCOM variation is calculated based on coupling the VCOM to one or more data lines of the electronic display. VCOM compensation is determined and applied to offset for the VCOM variation. Using the VCOM offset, subsequent pixel content for the one or more pixels is written using the compensated VCOM.

Content-based VCOM driving

The disclosure relates to systems and methods for reducing VCOM settling periods. A number of pixels is sub-divided into a plurality of regions. The pixels are configured to transmit light. A common voltage (VCOM) driving circuit is configured to drive a common electrode of the pixels. Moreover, each of a number of VCOM driving circuits includes a variable resistor configured to be driven to a resistance level based at least in part on which region of the plurality of regions includes an active pixel within the region. Furthermore, a resistance level is set and based at least in part on where the active pixel is located.

Multi-zoned variable VCOM control

Systems and methods are provided for improving displayed image quality of an electronic display with reduced power consumption. In some embodiments, a display pixel in the electronic display includes a pixel electrode and a common electrode. A pixel electrode driver electrically coupled to the first display pixel writes the display pixel by supplying a pixel voltage signal to the pixel electrode. A common electrode driver electrically coupled to the common electrode includes a power amplifier that supplies a common voltage signal to the common electrode to predictively offset net charge accumulation expected in the common electrode; a first power supply rail selectively connectable to the power amplifier based on a target voltage of the common voltage signal; and a second power supply rail selectively connectable to the power amplifier based on the target voltage, in which the first and second power supply rails supply different voltages when connected.

Content dependent common voltage driver systems and methods

A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Growing community of inventors

San Jose, CA, United States of America

Fenghua Zheng