Intel Corporation

Cisco Technology, Inc.

Arista Networks, Inc.

Stellar Cyber, Inc.

Feng Zhu

Xin Guo

Pranav Kalavade

David J Pelster

Aliasgar S Madraswala

Yogesh B Wakchaure

Myron Loewen

Shyam Sunder Raghunathan

Brennan A Watt

Krishna Kumar Parat

Ravi H Motwani

Premkumar Jonnala

Simon Francis Capper

Iwen Chao

Kartik Chandran

Sriram Chidambaram

Dehua Huang

Nagarani Chandika

Eric L Hoffman

Kyle Haight

Di Wang

Hemanth Murthy

Jing-Jing Li

Aimei Wei

Dan Mihai Florea

Bimohit Bawa

A computer-implemented method includes generating a hash key using a number of least significant bits (LSBs) for indexing an indirection table in a computing system including multiple processing cores. In generating the hash key, symmetry constraints for a request packet and a response packet through a same communication channel are computed. The symmetry constraints include at least a condition where the LSBs of a hash value corresponding to a source or destination IP address of the request packet are equal to the LSBs of a hash value corresponding to a destination or source IP address of the response packet, wherein the LSBs of the hash value of the request and response packets are of a number same as the number of LSBs used for indexing the indirection table. A string of bits are subjected to the symmetry constraints and adjusted to satisfy the symmetry constraints to generate the hash key.

LSB based symmetric receive-side scaling

Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

Techniques for non-volatile memory page retirement

A method and apparatus of a network element that updates an interface list of a multi-link group of a network element is described. In an exemplary embodiment, a network element receives an indication that the interface list for the multi-link group on a network element is to change. In addition, the interface list includes a first set of interfaces. The network element further includes an address table having a plurality of address entries, where each of the plurality of address entries includes an address, a multi-link nexthop, and a tag group reference. The tag group reference references an entry in a tag group table, where a tag group entry includes a tag group identifier and a tag group set of interfaces. The network element further receives a second set of interfaces. The network element additionally updates the interface list for the tag group entry to include a second set of interfaces. Furthermore, the network element transmits data with the multi-link group using the second set of interfaces.

Updating interface list of multi-link group

Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

Method and apparatus for improving immunity to defects in a non-volatile memory

Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

Method and apparatus for defect management in a non-volatile memory device

Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC). The PDCis set to a logical AND of the PDCand a first result of a first sense operation. The PDCis set to a logical AND of the PDCand an inverse value of the PDC. The PDCis set to a logical AND of the SDC and the PDC. The PDCis set to a logical AND of the PDCand an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC. The SDC is set to a logical OR of the SDC or the PDC. The PDCis set to a logical AND of the PDCand a third result of a third sensing operation.

Methods and apparatus to preserve data of a solid state drive during a power loss event

Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell.

Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Defect management policies for NAND flash memory

Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

Dynamically compensating for degradation of a non-volatile memory device

A DHCP proxy agent is provided to send on behalf of a static host a DHCP request so that an access layer security feature such as DHCP snooping/IPSG can be applied to the static host and/or in a mixed static IP and DHCP environment.

Growing community of inventors

San Jose, CA, United States of America

Feng Zhu