Taiwan Semiconductor Manufacturing Comp. Ltd.

Chung-shan Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense

National Chung Shan Institute of Science and Technology

Chung-shan Institute of Science and Technology, Armaments Bureau, M.n.d

Customs Administration, Ministry of Finance, R.o.c.

Chung-san Institute of Science and Technology, Armaments, Bureau, Ministry of National Defense

Directorate General of Customs, Ministry of Finance R.o.c.

Feng-Yu Chang

Mei-Yun Wang

Kuo-Yi Chao

Chao-Hsun Wang

Chen-Yuan Kao

Po-Yu Huang

Shih-Che Lin

Yu-Feng Yin

Rueijer Lin

Wei-Jung Lin

Ming-Town Lee

Tain-Wen Suen

Tung-Jung Hsu

Yu-Cheng Chang

Yu-Shan Lin

Jia-En Lee

Fu-Kai Yang

Jyu-Horng Shieh

Sheng-Liang Pan

Shu-Huei Suen

Shao-Jyun Wu

Chia-Yang Hung

Chun-Fu Lin

Jack Kuo-Ping Kuo

Yu-San Lin

Jen-Chi Liao

Pang-Sheng Chang

Chia-Sheng Chang

Wei-Yi Tseng

Po-Chang Chen

A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Forming metal contacts on metal gates

Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Different via configurations for different via interface requirements

Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

Conductive features having varying resistance

A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Vertical interconnect features and methods of forming

A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity &#x3b2;-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity &#x3b2;-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity &#x3b2;-W phase. The &#x3b2;-W converts to a low-resistivity &#x3b1;-phase of tungsten in the regions not pre-treated with impurities.

An electronic bolt using wireless communication is disclosed and includes a bolt coil formed on a surface of the bolt circuit board, and configured to receive a wireless energy from an electronic seal; and a chip electrically connected to the bolt coil, and configure to generate a wireless signal containing a unique identification to the bolt coil when the chip is driven by the wireless energy; a holder configured to fix and support the bolt circuit board; and a bolt housing configured to contain the bolt circuit board and the holder; wherein the electronic bolt is locked or unlocked with the electronic seal when the unique identification is confirmed by the electronic seal.

Near field communication electronic bolt

A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.

A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Metal contacts on metal gates and methods thereof

A composite type multi-mode electronic seal includes the bolt, the bolt male pedestal and the communication control part, and the advantage of the composite type multi-mode electronic seal containing the passive electronic seal containing the bolt and the bolt male pedestal and the active electronic seal containing bolt, the bolt male pedestal and the communication control part. Thereby, the present invention has the advantages and preferred result of the active and passive electronic seal, and can help the container cars, bonded cars, trucks and the like to perform the goods transmission, and it still perform the data read and data report according to the different RFID identification equipments built by every country's custom so to achieve the purpose of effectively recording the broken elements, instantly reporting and preventing smuggling.

Composite type multi-mode electronic seal

Growing community of inventors

Kaohsiung, Taiwan

Feng-Yu Chang