Texas Instruments Corporation

Feng Ying

Haydar Bilhan

Gary Lee

Gonggui Xu

Ching-Yuh Tsay

Ramesh Chandrasekaran

Lieyi Fang

Yong Han

Erkan Bilhan

M C Ramesh

Franco Maloberti

Karl H Renner

Charles M Branch

Weider Peter Chang

Kuok Y Ling

Walter Heinrich Demmer

Jason Meiners

James E Nave

Xiaopeng Li

Shereef Shehata

Towfique Haider

Xiaodong Wu

Huimin Xia

Xucheng Wang

Viet Dinh

A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.

MPEG-2 transport stream packet synchronizer

System and method for an all-digital audio receiver for a BTSC MTS audio signal or other composite signal that is FM modulated. A preferred embodiment comprises a digital FM demodulator for receiving an analog to digital quantized SIF signal and performing demodulation and outputting a composite audio signal, and a digital audio processor for decomposing the composite audio signal into at least the SAP, stereo and monaural signals for audio reproduction. In a preferred embodiment, the digital audio processor is a programmable digital signal processor. In a preferred embodiment, the digital FM demodulator and the digital audio processor are implemented as an integrated circuit. Methods for processing the audio signal using the digital processors of the invention are provided.

Method and apparatus for digital MTS receiver

An apparatus, system and method for clamping a video signal input to a coupling capacitor () for providing a clamping voltage. A charging current is applied to the capacitor () via an amplifier () having a first input () coupled with the capacitor output and a second input () coupled to a reference potential, the amplifier () is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Clamping circuit for video signals

A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit () includes a clamping capacitor () that couples to an automatic clamping circuit portion () to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (V) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion () connects to the customizable clamping circuit portion () to clamp any portion of the video input signal to a second predetermined reference voltage (V) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer () connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Clamping circuit with wide input dynamic range for video or other AC coupled signals

An image processing apparatus () for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the offset and optical black correction circuit is programmable. The present invention includes a first circuit () to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler () coupled to a first programmable gain amplifier (). An adder () connects between the first programmable gain amplifier () and a second gain amplifier () for adding in the optical black offset to the optical black signal input from the CCD. A second circuit () includes a reverse programmable gain amplifier () connected to the output of the second programmable gain amplifier () to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier (). The second circuit () also includes an integrator () coupled to the reverse programmable gain amplifier () to integrate the difference between the incoming signal and the desired optical black value. The second circuit () couples to the adder () to add the positive and negative difference to the optical black signal. An analog-to-digital converter () converts the sampled signal for further processing at the output of the image processing apparatus ().

Analog optical black clamping circuit for a charge coupled device having wide programmable gain range

A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier () may include a capacitive switching circuit (), a capacitive switching circuit (), and an operational amplifier (). Capacitive switching circuits (and) may receive an analog input voltage through sample switches (and). Capacitive switching circuit () receives an output from operational amplifier () through feedback switch (). The programmable gain amplifier () may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

Method and apparatus for exponential gain variations with a linearly varying input code

A shunt-shunt feedback current to voltage converter ( ) including a compensating current ( ) provided to the output of the amplifier ( ) which mirrors the input current ( ) advantageously removing the loading effects of the feedback resistor (R ) to the amplifier ( ). A current steering DAC ( ) is utilized in conjunction with a plurality of polarity control switches ( ) to provide either a source current or a sink current to the amplifier input, and a complementary sink current or source current, respectively, to the output of the amplifier such that the amplifier ( ) does not provide any current to the feedback resistor. Thus, DC gain of the amplifier is maintained. The current steering DAC ( ) provides a matched source current and sink current to achieve this architecture.

Canceling feedback resister loading effect in a shunt-shunt feedback circuit

An image processing apparatus for charge coupled device (CCD) and video inputs in a digital camera or for a digital camcorder is disclosed which provides optical black and offset correction for CCD inputs. A sampling circuit, including correlated double sampler (CDS) ( ) and programmable gain amplifier ( ), samples the image input signal and the video input signal. CDS ( ) includes a single-ended amplifier ( ) and a differential amplifier ( ). The single-ended amplifier ( ) functions such that it is only operable during an CCD signal input; otherwise, the single-ended amplifier ( ) is bypassed such that a video signal is only sampled by the differential amplifier ( ). For CCD signals, the single-ended amplifier ( ) samples the reference level of the pixel and holds it during the video interval. The differential amplifier ( ) samples both the output of the single ended amplifier ( ) and the video level of the same pixel. Overall, the CDS ( ) subtracts these levels and converts the difference to a differential output to improve signal to noise performance and dynamic range. An analog-to-digital converter ( ) converts the sampled signal and feeds this digital sample to a digital correction circuit ( ) where optical black level, hot and cold pixels, and line noise are removed.

CMOS analog front end architecture with variable gain for digital cameras and camcorders

An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section coupled with an input locus and a digital signal section coupled between the analog signal section and an output locus. The signal conversion devices receive sampled analog signals that are phase-offset by a first phase difference. Two feedback devices are each coupled between the output locus of one signal conversion device and the analog signal section of the other signal conversion device to convey feedback signals that are phase-offset by a second phase difference. The first phase difference and the second phase difference cooperate to affect power density spectrum of a resultant digital output signal at at least one predetermined frequency. The resultant digital output signal is a summing of a digital output signals presented by the two signal conversion devices at their output loci.

Apparatus for generating at least one digital output signal representative of an analog signal

A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit ( and ) for receiving an input signal and a symmetry circuits ( and ) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (I ) provides current to a common node (N ) in which current is advantageously steered to each half circuit ( and ) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Delay circuit with current steering output symmetry and supply voltage insensitivity

A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is disclosed. According to one embodiment, the programmable gain amplifier ( ) may include a capacitive switching circuit ( ), a capacitive switching circuit ( ), and an operational amplifier ( ). Capacitive switching circuits ( and ) may receive an analog input voltage through sample switches ( and ). Capacitive switching circuit ( ) receives an output from operational amplifier ( ) through feedback switch ( ). The programmable gain amplifier ( ) may include a few additional unit capacitors which can allow larger gain ranges or more steps for a given range without a large increase in chip size.

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Plano, TX, United States of America

Feng Ying