United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Feng-Yi Chang

Fu-Che Lee

Chieh-Te Chen

Chun-Lung Chen

Kun-Yuan Liao

Chia-Lin Lu

Shih-Fang Tzou

Yu-Cheng Tung

Ying-Chih Lin

Yi-Ching Chang

Jiunn-Hsiung Liao

Chih-Sen Huang

Gang-Yi Lin

Ming-Feng Kuo

Wei-Hao Huang

Yi-Wang Zhan

Ching-Wen Hung

Chien-Cheng Tsai

Li-Chiang Chen

Shang-Yuan Tsai

Chih-Wen Feng

Ching-Pin Hsu

Hsuan-Hsu Chen

Chun-Hsien Lin

Po-Chao Tsao

Pei-Yu Chou

Feng-Ming Huang

Kai-Lou Huang

Yi-Wei Chen

En-Chiuan Liou

Yi-Po Lin

Shi-Xiong Lin

Chien-Ting Lin

Hsien-Shih Chu

Chia-Liang Liao

Hsin-Yu Chiang

Chin-Hsin Chiu

Chi-Mao Hsu

Yu-Tsung Lai

Shui-Yen Lu

Tsuo-Wen Lu

Chien-Ting Ho

Shu-Yen Chan

Ching-Ling Lin

Ming-Tsung Chen

Hsiao-Pang Chou

Tien-Chen Chan

Ger-Pin Lin

Chang-Chi Huang

Yu-Ching Chen

Kuan-Chun Lin

Chien-Ming Lu

Shih-Kuei Yen

Cheng-Hsing Chuang

Yu-Hsiang Hung

Yi-Hui Lee

Chih-Wei Yang

Jia-Rong Wu

Chia-Wei Huang

Shu-Ru Wang

Chien-Hao Chen

Ying-Cheng Liu

Wei-Lun Hsu

Wei-Hsin Liu

Ming-Te Wei

Chia-Hung Wang

Chia-Hsun Tseng

Jui-Min Lee

Po-Han Wu

Chun-Ting Yeh

Yu-Ting Hung

Jyh-Cherng Yau

Wen-Chieh Lu

Yi-Kuan Wu

Chiung-Lin Hsu

Meng-Chia Tsai

A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Semiconductor memory device

A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Semiconductor device

A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

Patterned structure

A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

Contacts and method of manufacturing the same

A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.

Semiconductor memory device having a multilayer dielectric structure with a retracted sidewall below a bit line

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Method of forming semiconductor device

A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

Buried word line of a dynamic random access memory and method for fabricating the same

A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.

Capacitor structure

A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Semiconductor device and method of forming the same

A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.

A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.

Capacitor structure and fabrication method thereof

A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.

Semiconductor device and manufacturing method thereof

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Tainan, Taiwan

Feng-Yi Chang