International Business Machines Corporation

Feng Xue

Jeffrey George Komatsu

Jung H Yoon

Paul Anthony Zulpa

Wen Wei Low

Steven B Gold

Yvonne Chii Yeo

Jun Jiang

Michael J Whitney

Matthew Stephen Kelly

WeiFeng Zhang

Richard Burton Finch

Lei Yang

Ai Kiar Ang

Lin Zhao

Robert A DiMarco

Zhipeng Wang

Christian Nugraha

Viktor Bruzsa

David J Gifford

Ferenc Simon

Vincent J Giancaspro

Muhammad Muneer Kader Shareiff

Ferenc Tokodi

Yin Mon Zun

Melinda Quiambao Litonjua

Lay Him Yeo

Weng Foong Khong

Julian Reyes

John Scott Bacon

Aaron Civil

Ding Guo Xiong

A computer-implemented method, according to one approach, includes: detecting new data generated at a first edge node, and causing a first copy of the new data to be transferred to a central data storage location in real-time. A second copy of the new data is also stored in a first location at the first edge node. In response to a predetermined condition being met, a determination is made as to whether any information in the first copy of the new data transferred is missing at the central data storage location. The first copy of the new data is removed from the first location at the first edge node in response to determining that no information in the first copy of the new data transferred is missing at the central data storage location.

Processing and archiving data from edge nodes across distributed systems

Aspects of the invention include receiving, by a processor, operational data, determining a dashboard template including a set of windows arranged within the dashboard template, the dashboard template determined based at least in part on the operational data, determining a set of key performance indicators (KPIs), generating a command center dashboard having a layout including one or more windows from the set of windows, wherein each of the one or more windows displays an application associated with each KPI in the set of KPIs, and projecting, through a display device, the command center dashboard.

Semi-virtualized portable command center

A computer-implemented method includes assigning an auditor weight to each user of a plurality of users. A plurality of audit data is received from the plurality of users, where each audit data is associated with a respective user and includes a set of user ratings for an audit. Final ratings are generated for the audit, with a respective final rating for each item in the audit. Generating the final rating of a first item in the audit includes identifying, in the audit data, user ratings for the first item. The user ratings for the first item include a respective user rating of the first item from each user. Generating the final rating of a first item further includes calculating the final rating of the first item based on a weighted combination of the plurality of user ratings for the first item, according to the respective auditor weight of each user.

Advising audit ratings in a multiple-auditor environment

In an approach for storage optimization for products manufacturing, a processor pulls parts data for a set of part numbers. A processor calculates an average shelf time for each part number of the set of part numbers. A processor calculates a priority index for each part number of the set of part numbers based on the average shelf time for each part number of the set of part numbers. A processor determines a category for each part number of the set of part numbers based on the priority index for each part number of the set of part numbers and a quantity of parts cumulative percentage for each part number of the set of part numbers.

Storage optimization for products manufacturing

A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization

A method includes receiving a training data set for a first plurality of assemblies, wherein the training data set includes a plurality of components for each of two or more types of components of the first plurality of assemblies. The method analyzes the training data set for the first plurality of assemblies. Responsive to receiving a set of product component information for a second plurality of assemblies, the method creates a graded product cluster template for the second plurality of assemblies based on the analyzed training data for the first plurality of assemblies. The method sends the graded product cluster template to an automated manufacturing device, wherein the automated manufacturing device manufactures a first assembly from the second plurality of assemblies based on the graded product cluster template.

Parts matching for improved manufacturing assembly

A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

A method for determining quality includes receiving supplier quality data from a supplier. The supplier quality data includes discrete quality data. The supplier quality data is for a quantity of a component supplied to a company or for a service provided on behalf of the company over a supplier measurement period. The method includes aggregating quality data from two or more suppliers. The quality data is for the supplied component or provided service over a baseline time period. The method includes determining a quality benchmark using the aggregated quality data and setting one or more alarm levels. The alarm levels are based on the quality benchmark of the aggregated quality data. The method includes determining supplier quality level for the supplier for the supplier measurement time period. The supplier quality is based on the supplier quality data. The method includes determining if the supplier quality data exceeds an alarm level.

Automated data-driven closed-loop-feedback method for adaptive and comparative quality control in a discrete data aggregation environment

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Singapore, Singapore

Feng Xue