Realtek Semiconductor Inc.

Skyworks Solutions, Inc.

Emcore Corporation

Feng Shi

Stephan Ten Brink

Turgut Sefket Aytur

Ravishankar H Mahadevappa

Ran Yan

Sang Lee

Mustafa Altintas

An optical fiber data communications network in which an electro-optical transceiver couples a plurality of serial electrical data buses over a single bidirectional optical fiber link, and includes a controller that functions by oversampling the digital electrical signal on each of such buses, multiplexes them, and converts the signal into a high speed optical signal for transmission over an optical fiber.

Data communications system including an optical fiber data link disposed between serial bidirectional electrical data busses

A method of generating a hazard-free representation of a logic circuit that can leverage the powerful and mature synchronous-circuit CAD synthesis tools. In a representative embodiment of the method, an initial representation of a specified asynchronous logic circuit is synthesized using one of such CAD tools. The initial representation is then analyzed to identify hazardous transitions and modified, e.g., by iteratively inserting additional logic aimed at preventing the identified hazardous transitions from producing glitches, until a hazard-free representation of the specified asynchronous logic circuit is produced.

Detection and removal of hazards during optimization of logic circuits

Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.

Deinterleaver and dual-viterbi decoder architecture

Growing community of inventors

Irvine, CA, United States of America

Feng Shi