Sandisk Technologies Inc.

Micron Technology Incorporated

Sandisk Corporation

Advanced Micro Devices Corporation

Wuxi Petabyte Technologies Co, Ltd.

Intel Corporation

Paypal, Inc.

Other

Vormetric, Inc.

Feng Q Pan

Ramin Ghodsi

Jonathan Huynh

Trung Pham

Qiang Tang

Colin Stewart Bill

Bo Lei

Qui V Nguyen

Sung-En Wang

Khin Htoo

Shankar Guhados

Kiran Pangal

Jun Wan

Khandker N Quader

Edward V Bautista, Jr

Davide Mantegazza

Jaekwan Park

Yuxin Wang

Byungki Woo

Hernan Adolfo Castro

Derchang Kau

Long C Pham

Weng Fook Lee

Alexander K Mak

Khanh T Nguyen

Shiwen Shen

Danielle Zhu

Mark Alan Helm

Michele Piccardi

Shigekazu Yamada

Albert Chang

Man Lung Mui

Kazuhiro Kurihara

Darlene G Hamilton

Xiaojiang Guo

Ravi S Sunkavalli

Tien-Chien Kuo

Jun Wang

Prashant S Damle

Zhenyu Lu

Chi-Ming Wang

Kalyan C Kavalipurapu

Allahyar Vahidimowlavi

Jae-Kwan Park

Yongke Sun

Sagar Magia

Hanmant Pramod Belgal

Santosh K Yachareni

Tat-Kwan Edgar Yu

Jing Jing Chen

Marco Cazzaniga

Prashanti Govindu

Viswakiran Popuri

Azrul Halim

Jonathan Shi-Chang Su

Sri Sudarsan

Jiang Yin

Cairong Hu

Gyuwan Kwon

Weng F Lee

A unified model for a neural network can be used to predict a particular value, such as a customer value. In various instances, customer value may have particular sub-components. Taking advantage of this fact, a specific learning architecture can be used to predict not just customer value (e.g. a final objective) but also the sub-components of customer value. This allows improved accuracy and reduced error in various embodiments.

Unified artificial intelligence model for multiple customer value variable prediction

Embodiments relate to digital low-dropout (DLDO) with fast feedback and optimized frequency response. Certain embodiments may relate more particularly to ferroelectric memory circuit configurations. For example, a low dropout regulator may include a first circuit path configured to regulate an input voltage to an output voltage at a load, wherein the first path comprises a first transistor. The apparatus may also include a second circuit path configured to feed back an error signal based on the input voltage and the output voltage, wherein the second circuit path comprises an error amplifier.

Digital low-dropout regulator (DLDO) with fast feedback and optimized frequency response

Embodiments of the present disclosure relate to an architecture for random access memory (RAM) circuit configurations. For example, certain embodiments relate to a ferroelectric RAM (FRAM) read only memory (ROM) wordline architecture. A method for power-on reset of a memory can include powering on the memory. The method can also include reading a first flag in a first bit of a first configuration wordline of the memory, wherein the first configuration wordline is one of a plurality of redundant configuration wordlines. The method can further include reading, when the first flag indicates the first configuration wordline is valid, a predetermined number of bytes of the wordline. The method can additionally include configuring operations of the memory based on the predetermined number of bytes, when the first flag indicates the first configuration wordline is valid.

Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines

While artificial neural networks can be used to predict particular values in certain contexts, convolutional neural networks are not typically used in these contexts&#x2014;instead they may be employed for image recognition. However, raw transactional data may be structured to take advantage of convolutional neural network (CNN) techniques by arranging the data such that correlations are increased between nearby other data. In arranging data in this manner, the structured CNN (SCNN) can operate efficiently without having to make use of engineered data features, the generation and maintenance of which can be a time-consuming process.

Convolutional neural networks for variable prediction using raw data

Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

Apparatuses and methods for segmented SGS lines

Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, an apparatus comprises transistors, and a charge sharing circuit coupled to the transistors through gate terminals of the transistors. The charge sharing circuit comprises a programmable electrical source, a first switch coupled to the programmable electrical source, a capacitor coupled to the first switch, and a second switch coupled to the capacitor, the first switch, and the gate terminals of the transistors. The programmable electrical source is configured to provide electrical charges to the capacitor when the first switch is turned on and the second switch is turned off. The capacitor is configured to provide at least a portion of the electrical charges to the gate terminals of the transistors when the first switch is turned off and the second switch is turned on.

Memory and calibration and operation methods thereof for reading data in memory cells

A wordline driver may include the following: a first transistor having a first node at the input and a second node at an input voltage; a second transistor having a first node at the input node, a second node at a third node of the first transistor, and a third node at ground; a third transistor having a first node at the input voltage, a second node at the first internal node and a third node at a second internal node; a fourth transistor having a first node at an internal node, a second node at a boosted voltage, and a third node at a wordline; a fifth transistor having a first node at an internal node, a second node at the wordline, and a third node at ground; and a sixth transistor between the wordline, the boosted voltage, and the second internal node.

Efficient ferroelectric random-access memory wordline driver, decoder, and related circuits

Embodiments of operation methods of ferroelectric memory are disclosed. In an example, a method for reading ferroelectric memory cells is disclosed. The ferroelectric memory cells include a first set of ferroelectric memory cells and a second set of ferroelectric memory cells. In a first cycle, first data in a first ferroelectric memory cell of the first set of ferroelectric memory cells is sensed. In a second cycle subsequent to the first cycle, the sensed first data is written back to the first ferroelectric memory cell, and second data in a second ferroelectric memory cell of the second set of ferroelectric memory cells is simultaneously sensed.

Operation methods of ferroelectric memory

Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Apparatuses and methods for charge pump regulation

Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Apparatuses and methods for reducing read disturb

Embodiments of methods for operating ferroelectric memory cells are disclosed. In one example, a method for writing a ferroelectric memory cell is provided. The ferroelectric memory cell includes a transistor and N capacitors. The transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective one of N plate lines in parallel. A plate line signal pulsed between 0 V and Vdd is applied to each of the N plate lines according to a plate line time sequence. A bit line signal pulsed between 0 V and the Vdd is applied to the bit line according to a bit line time sequence to write a valid state of data into the N capacitors. The data consists of N+1 valid states that can be written into the N capacitors. The valid states of the data are determined based on the plate line time sequence. The bit line time sequence is determined based on the valid state of the data written into the N capacitors.

Methods for operating ferroelectric memory cells each having multiple capacitors

There are provided systems and methods for intelligent online account lifecycle maintenance through automated event monitoring. A user may utilize an online account with the service provider to perform various actions and generate account usage data. Based on the account usage data, such as a length the account has been in service, amount the account is used, and other lifecycle data for the account, a user action may be taken with respect to the account. For example, the user action may correspond to a recommendation for the user for a feature that the user may utilize with the account that other similar users utilize, but the user does not. The recommendation may be based on whether the user is a new or ongoing user. A communication channel to send the action to the user may be determined based on a most likely to view channel.

Intelligent online account lifecycle maintenance through automated event monitoring

Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

Apparatuses for modulating threshold voltages of memory cells

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Boise, ID, United States of America

Feng Q Pan