Shanghai Huali Microelectronics Corporation

Shanghai Huali Integrated Circuit Corporation

Cisco Technology, Inc.

Feng Ji

Zhi Tian

Lei Li

Tao Liu

Alpesh Umakant Bhobe

Haoyu Chen

Jianquan Lou

Qiwei Wang

Jinghan Yu

Yingchun Shu

Youcun Hu

Jinshuang Zhang

Li Xiaogang

Yuwen Chen

Qichao Liang

Jiacheng Wen

Chen Peng

Chaos Zhang

The present application discloses a method for manufacturing a semiconductor device, which includes the following steps: step 1: forming first gate structures on a semiconductor substrate; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove; step 3: performing a stress memorization process, including step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer the stress of the stress dielectric layer to a channel region; step 33: removing the stress dielectric layer. The present application can increase the effect of transferring the stress of the stress dielectric layer to the channel region, thereby increasing the mobility of channel carriers.

Method for manufacturing a super flash memory

The present application discloses a low voltage triggering silicon controlled rectifier which includes: an N well and a P well forming a PN junction, a first P+ region formed in the N well and connected to an anode, and a first N+ region formed in the P well and connected to a cathode. A second P+ region is formed in the N well at the PN junction and diffuses into the P well. A second N+ region is formed in the P well at the PN junction and diffuses into the N well. A first gate structure connected to the anode is formed at the surface of the N well between the first and second P+ regions; and a second gate structure connected to the cathode is formed at the surface of the P well between the first and second N+ regions.

Low voltage triggering silicon controlled rectifier

The present application discloses a cell structure of a super flash comprising: a word line gate, a floating gate, a control gate, and an erase gate. The floating gate comprises a first TiN layer located on a side face of the control gate and a second polysilicon layer formed at the top of the first TiN layer. The second polysilicon layer is in electric contact with the first TiN layer. The erase gate is located at the top of the second polysilicon layer, and the erase gate and the floating gate are spaced from each other by a second inter-gate dielectric layer therebetween. During erasing, the top angle of the second polysilicon layer generates point discharge, thereby reducing an erasing voltage. The present application also discloses a method for manufacturing a super flash.

Super flash and method for manufacturing same

The present disclosure provides a semiconductor device and a manufacturing method therefor. The manufacturing method for a semiconductor device is provided for forming through-holes in a semiconductor device, comprising: forming a plurality of shallow trench isolations in portions of a substrate corresponding to memory cell regions; forming a plurality of gates on surfaces of the portions of the substrate; forming spacers on side walls at both sides of the gates extending in the first direction; depositing a sacrificial layer on the memory cell region; removing portions of the sacrificial layer corresponding to the shallow trench isolations at memory cell drain, and depositing an isolation dielectric on the shallow trench isolations at the memory cell drain to form isolation strips; and removing the remaining sacrificial layer to form bottom through-holes in spaces formed after removing the remaining sacrificial layer.

Semiconductor device and manufacturing method therefor

An electromagnetic interference (EMI) gasket is provided that includes a resiliently-flexible and conductive outer shell, a cushioning element disposed in the outer shell, and at least one magnetic component disposed in the outer shell configured to magnetically couple to a conductive surface of an electronic device chassis.

Magnetic electromagnetic interference gasket

A method of manufacturing high performance metal-oxide-metal capacitor device that resolves problems with implementing high capacitance in the metal-oxide-metal region by filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and filling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor.

Manufacturing method of a high performance metal-oxide-metal

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Shanghai, China

Feng Ji