Juniper Networks, Inc.

Brilliant Telecommunications, Inc.

Mediatek USA Inc.

Brilliant Telecommmunications, Inc.

Feng Frank Pan

Charles Frederick Barry

Meenakshi S Subramanian

Tian Shen

DeviPrasad Natesan

Philip Kruzinski

David R Jorgensen

Reed A Parker

Tian (Alan) Shen

Guochun (George) Zhao

Guochun George Zhao

Young Suk Kim

Yasu Noguchi

Hank P Nguyen

Meenakshi Subramanian

Guochun Zhao

Deviprasad Natesan

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values

An apparatus and method of scheduling timing packets to enhance time distribution includes an improved apparatus in a system in which at least one of time and frequency information is derived based on information distributed in timing packets, at least some of the timing packets being transmitted by or received by the apparatus. The improvement includes a scheduling module that determines a first packet transmission time offset of a first timing packet based on a first predetermined identifier associated with the apparatus, and a second packet transmission time offset of a second timing packet based on the first packet transmission time offset and a timing packet spacing that is independent of the first predetermined identifier. The improvement further includes a transmission module that transmits the first timing packet based on the first packet transmission time offset, and the second timing packet based on the second packet transmission time offset.

Apparatus and method of scheduling timing packets to enhance time distribution in telecommunication networks

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

An apparatus comprises a matrix of thermoelectric devices for applying thermal gradients across an electronic component mounted in a PCB substrate within an enclosed housing. A matrix of thermosensitive devices are placed around the perimeter of the electronic component to measure thermal gradients associated with the component. A controller controls the matrix of thermoelectric devices based on the thermal gradients measured by the matrix of thermosensitive devices with a matrix of thermocouple coefficients.

Apparatus and method for thermal stabilization of PCB-mounted electronic components within an enclosed housing

An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.

Apparatus and method of synchronizing distribution of packet services across a distributed network

An apparatus and method are described for forwarding of packets with controlled delay. In one embodiment, the invention includes controlled delay queuing logic to hold a packet in a first class for a queuing time of at least a controlled delay value, and scheduling logic to determine whether to delay transmission of a packet in a second class to allow the transmission of the packet in the first class when the queuing time reaches the controlled delay value.

Apparatus and method of controlled delay packet forwarding

A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.

Processor-controlled timing generator for multiple image sensors

An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.

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San Jose, CA, United States of America

Feng Frank Pan