Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Feng-Chien Hsieh

Kuo-Cheng Lee

Yun-Wei Cheng

Cheng-Ming Wu

Wei-Li Hu

Hsin-Chi Chen

Ying-Hao Chen

Chi-Cherng Jeng

Volume Chien

Zhe-Ju Liu

Mu-Han Cheng

Chen Hsin-Chi

Ting-Hao Chang

Chia-Yen Hsu

Chun-Hao Lin

Ping Kuan Chang

Shih-Ciang Huang

Wang Chun-Ying

ChunHao Lin

A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Mid-manufacturing semiconductor wafer layer testing

The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Semiconductor structure and method of manufacturing the same

An image sensor device includes a semiconductor substrate having a first side, and a trench isolation structure dividing the substrate into sensing units. Each sensing unit includes a first gate electrode and a second gate electrode disposed on the first side, and a first pixel and a second pixel extending into the substrate and disposed between the first and second gate electrodes from a top view perspective. The first pixel is disposed under the second pixel and electrically connected to the first gate electrode, and the second pixel is electrically connected to the second gate electrode. A method of manufacturing a semiconductor structure includes forming a trench isolation in a semiconductor substrate; forming a first pixel in the substrate; forming a second pixel in the substrate over the first pixel; forming a first gate structure over the substrate; and forming a second gate structure over the second pixel.

A pixel sensor includes a transfer fin field effect transistor (finFET) to transfer a photocurrent from a photodiode to a drain region. The transfer finFET includes at least a portion of the photodiode, an extension region associated with the drain region, a plurality of channel fins, and a transfer gate at least partially surrounding the channel fins to control the operation of the transfer finFET. In the transfer finFET, the transfer gate is wrapped around (e.g., at least three sides) of each of the channel fins, which provides a greater surface area over which the transfer gate is enabled to control the transfer of electrons. The greater surface area results in greater control over operation of the finFET, which may reduce switching times of the pixel sensor (which enables faster pixel sensor performance) and may reduce leakage current of the pixel sensor relative to a planar transfer transistor.

Method for manufacturing image sensor including forming FinFET transfer gate having a plurality of channel fins above a p-type region

A pixel array includes a plurality of dark pixel sensors configured to generate dark current calibration information for a plurality of visible light pixel sensors included in the pixel array. The plurality of dark pixel sensors may generate respective dark current measurements for each of the plurality of visible light pixel sensors or for small subsets of the plurality of visible light pixel sensors. In this way, each of the plurality of visible light pixel sensors may be individually calibrated (or small subsets of the plurality of visible light pixel sensors may be individually calibrated) based on an estimated dark current experienced by each of the plurality of visible light pixel sensors. This may enable more accurate dark current calibration of the visible light pixel sensors included in the pixel array, and may be used to account for large differences in estimated dark currents for the visible light pixel sensors.

Pixel array including dark pixel sensors

A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

Semiconductor arrangement with isolation structure

The present disclosure provides an integrated circuit (IC) structure with a solar cell and an image sensor array. An integrated structure according to the present disclosure includes a first substrate including a plurality of photodiodes, an interconnect structure disposed on the first substrate, a first bonding layer disposed on the interconnect structure, a second bonding layer disposed on the first bonding layer, a second substrate disposed on the second bonding layer, and a transparent conductive oxide layer disposed on the second substrate.

Integration of solar cell and image sensor

A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Pixel array including time-of-flight sensors

An image sensor device is disclosed which includes a semiconductor layer having a first surface and a second surface, where the second surface is opposite to the first surface. The device includes a conductive structure disposed over the first surface, with a dielectric layer disposed between the conductive structure and the first surface. The device includes a first dielectric layer disposed over the second surface of the semiconductor substrate. The device includes a second dielectric layer disposed over the first dielectric layer. The device includes a color filter layer disposed over the second dielectric layer. In some embodiments, the thickness, refractive index, or both of the first dielectric layer and the thickness, refractive index, or both of the second dielectric layer may be collectively determined to cause incident radiation passing through the first dielectric layer and the second dielectric layer and to the plurality of pixels to have destructive interference.

Back side illuminated image sensor device with select dielectric layers on the backside and methods of forming the same

An image sensor device includes a substrate, photosensitive pixels, an interconnect structure, a dielectric layer, and a light blocking element. The photosensitive pixels are in the substrate. The interconnect structure is over a first side of the substrate. The dielectric layer is over a second side of the substrate opposite the first side of the substrate. The light blocking element has a first portion extending over a top surface of the dielectric layer and a second portion extending in the dielectric layer. The second portion of the light blocking element laterally surrounds the photosensitive pixels.

Image sensor device

A semiconductor arrangement is provided. The semiconductor arrangement includes a first photodiode in a substrate. The semiconductor arrangement includes a lens array over the substrate. A first plurality of lenses of the lens array overlies the first photodiode. Radiation incident upon the first plurality of lenses is directed by the first plurality of lenses to the first photodiode.

Semiconductor arrangement and method of making

A front-side peripheral region of a first wafer may be edge-trimmed by performing a first pre-bonding edge-trimming process. A second wafer to be bonded with the first wafer is provided. Optionally, a front-side peripheral region of the second wafer may be edge-trimmed by performing a second pre-bonding edge-trimming process. A front surface of the first wafer is bonded to a front surface of a second wafer to form a bonded assembly. A backside of the first wafer is thinned by performing at least one wafer thinning process. The first wafer and a front-side peripheral region of the second wafer may be edge-trimmed by performing a post-bonding edge-trimming process. The bonded assembly may be subsequently diced into bonded semiconductor chips.

Edge-trimming methods for wafer bonding and dicing

An image sensing apparatus is disclosed. The image sensing apparatus includes a pixel array and micro lenses disposed above the pixel array. The pixel array includes sensing pixels configured to capture minutia points of a fingerprint and positioning pixels configured to provide positioning codes.

Optical fingerprint sensor with enhanced anti-counterfeiting features

The present disclosure describes an image sensor device and a method for forming the same. The image sensor device can include a semiconductor layer. The semiconductor layer can include a first surface and a second surface. The image sensor device can further include an interconnect structure formed over the first surface of the semiconductor layer, first and second radiation sensing regions formed in the second surface of the semiconductor layer, a metal stack formed over the second radiation sensing region, and a passivation layer formed through the metal stack and over a top surface of the first radiation sensing region. The metal stack can be between the passivation layer and an other top surface of the second radiation sensing region.

Growing community of inventors

Pingtung, Taiwan

Feng-Chien Hsieh