Taiwan Semiconductor Manufacturing Comp. Ltd.

Feng-Cheng Yang

Yen-Ming Chen

Wei-Yang Lee

Sheng-Chen Wang

Chung-Te Lin

Meng-Han Lin

Han-Jong Chia

Sai-Hooi Yeong

Chia-Ta Yu

Kai-Hsuan Lee

Feng-Ching Chu

Yen-Ting Chen

Yu-Ming Lin

Ting-Yeh Chen

Bo-Yu Lai

Tzu-Hsiang Hsu

Sheng-Chih Lai

Yu-Wei Jiang

Cheng-Yu Yang

Wei-Yuan Lu

Hung-Chang Sun

Kuo-Chang Chiang

Jian-Hao Chen

I-Hsieh Wong

Teng-Chun Tsai

Bo-Feng Young

Kuo-Feng Yu

Shih-Hao Lin

Chia-Jung Hsu

Yen-Chieh Huang

Hui-Chi Chen

TsuChing Yang

Chia-Wei Chen

Shan-Mei Liao

Chen-Jun Wu

Chi On Chui

Ziwei Fang

Hsueh-Chang Sung

Yi-Ching Liu

Li-Li Su

Chien-Wei Lee

Chih-Yu Hsu

Chieh-Fang Chen

Tsu Ching Yang

Tsung-Lin Lee

Yih-Ann Lin

Hui-Hsien Wei

Bo-Cyuan Lu

Pin-Cheng Hsu

Gin-Chen Huang

Chia-Ling Chan

Tzu-Ching Lin

Yen-Chung Ho

Chia-Jung Yu

Yong-Jie Wu

Kuei-Lun Lin

Chun-An Lin

Yi-Hsiu Liu

Chia-Chun Lan

Yu-Chia Liang

Chii-Horng Li

Katherine H Chiang

Ying-Ho Chen

Yen-Ru Lee

Chien-I Kuo

Chun-Fu Cheng

Chia-en Huang

Nuo Xu

Han-Wei Wu

Chih-Hsiang Huang

Neil Quinn Murray

Hsiao-Chiu Hsu

Sai-hooi Yeong

Yu-Chien Chiu

Jyun-Chih Lin

Cheng Hong Yang

Hung Lo

Mei-Yun Wang

Chia-En Huang

Fu-Kai Yang

Dian-Hau Chen

Da-Yuan Lee

Chen-Ming Lee

Chi-On Chui

I-Wen Wu

Cheng-Hao Hou

Ya-Yun Cheng

Chih-Hung Wang

Tsung-Da Lin

Kuo Chang Chiang

LI-Li Su

Chieh-Yi Shen

Chih-Hsin Yang

Yea-Dean Sheu

Wen-Ling Lu

Chih-Hsuan Cheng

Huang-Chin Chen

Shih-Hsuan Chien

A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Flexible merge scheme for source/drain epitaxy regions

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

Semiconductor device with phosphorus-doped epitaxial features

A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Memory device, semiconductor device and manufacturing method of the memory device

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

Dielectric inner spacers in multi-gate field-effect transistors

A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.

Memory cell having source or drain electrode with kink portion, memory array and manufacturing method thereof

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Self-aligned contact air gap formation

A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

Three-dimensional memory device with word lines extending through sub-arrays, semiconductor device including the same and method for manufacturing the same

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Semiconductor structure and method for forming thereof

A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

Epitaxial structures for fin-like field effect transistors

A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

Semiconductor device

In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

High selectivity isolation structure for improving effectiveness of 3D memory fabrication

A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Protective liner layers in 3D memory structure

Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Integrated circuit device with source/drain barrier

Growing community of inventors

Hsinchu County, Taiwan

Feng-Cheng Yang