Realtek Semiconductor Inc.

Feng-Cheng Chang

Bing-Juo Chuang

Xiao-Guo Zheng

Wei-Xiong He

Fei Xu

Pei-Si Wu

Disclosed is a test system including a transmitter, a receiver, a measuring circuit, and a control circuit. The transmitter is coupled to the receiver in a DC coupling manner, and includes: a signal input circuit determining an output signal according to an input signal; a current source coupled between the signal input circuit and a low power-supply terminal and configured to determine a total current passing through the signal input circuit in a non-open/short-circuited condition; and a signal output wire circuit outputting the output signal for a performance test. The receiver includes: an impedance circuit coupled to the signal output wire circuit; and a coupling circuit coupling the impedance circuit with a high power-supply terminal. The measuring circuit measures a target current/voltage between the high power-supply terminal and low power-supply terminal to generate a measurement result. The control circuit determines whether the transmitter/receiver is open/short-circuited according to the measurement result.

Test system, transmitter, and receiver capable of executing multiple tests based on DC coupling configuration

A test system includes a transmitter, capacitor, and receiver. The transmitter includes: an output circuit coupled to the receiver via the capacitor; a transmitting circuit transmitting a predetermined signal to a pad of the output circuit during a first test; a signal generator outputting a first signal and second signal to the pad during a first process and second process of a second test; and a comparator comparing the pad's signal with a reference signal in the first process and second process to determine whether the second test passes. The receiver includes: an input circuit coupled to the transmitter via the capacitor; a switch coupled between the input circuit and a receiving circuit to be conducting in the first test and second process and nonconducting in the first process; and the receiving circuit determining whether the first test passes according to the predetermined signal and assisting the capacitor in discharging.

Test system, transmitting device, and receiving device capable of performing multiple tests in AC coupling mode

Disclosed is a USB Type-C switching circuit configured for arranging a plurality of signals of a USB Type-C connector. The USB Type-C switching circuit can be used in products having DisplayPort Alternate mode, and includes a plurality of signal receivers/receivers, a plurality of series-parallel transforming circuits and a multiplexer. The signal receivers/receivers are connected to the USB Type-C connector to receive/transmit signals. The series-parallel transforming circuits are connected to the signal receivers/receivers to convert the signals between a parallel domain and a serial domain. The multiplexer is connected to the series-parallel transforming circuits to arrange the signals in the parallel domain according to a control signal.

USB type-C switching circuit

The present disclosure provides a crystal-less clock and data recovery (CDR) circuit and a frequency detection method thereof. The CDR circuit includes a clock generator and a frequency detection module. The clock generator is operable to generate a clock signal. The frequency detection module coupled to the clock generator is configured for outputting a control signal to the clock generator to increase or decrease the frequency of the clock signal according to a data signal received and a transition density.

Clock and data recovery circuit and frequency detection method thereof

This invention discloses circuits and methods for generating a pixel clock. The circuits utilize an image signal of a first format to generate a pixel clock, which can be utilized to generate an image signal of a second format. The circuits include a reference clock generation circuit, an image processing circuit, and a clock adjustment circuit. The reference clock generation circuit generates a reference clock. The image processing circuit processes the image signal of the first format to generate a control signal. The clock adjustment circuit, which is coupled to the reference clock generation circuit and the image signal processing circuit, generates the pixel clock according to the reference clock and the control signal. The control signal is substantially a periodic signal, whose frequency is proportional to the frequency of a synchronization signal of the image signal of the second format.

Pixel clock generation circuit and method thereof

The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal.

Growing community of inventors

Hsinchu, Taiwan

Feng-Cheng Chang