Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Feng Chen

Lap Chan

Lup San Leong

Wang Ling Goh

Charles Lin

Kok Hin Teo

Alex See

Qiong Li

Juan Boon Tan

Huang Liu

John Leonard Sudijono

Victor Seng Keong Lim

Alan Cuthbertson

Peter Chew

Arthur Ang

Seng-Keong Victor Lim

Edwin Goh

Dong Sheng Liu

Subbiah Chettiar Mahadevan

Kong Hean Lee

Paul Proctor

Cing Gie Lim

Kok Hiang Tang

Cheng-Hou Loh

Cing Ge Lim

Arthur Khoon Siah Aug

Rick Teo

An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.

Integrated circuit system with dummy region

In one embodiment, a dielectric layer () overlying a semiconductor substrate () is uniformly polished. During polishing, the perimeter () of the semiconductor substrate () overlies a peripheral region () of a polishing pad () and an edge portion () of the front surface of semiconductor substrate () is not in contact with the front surface () of the polishing pad (), in the peripheral region (). As a result, the polishing rate at the edge portion () of the semiconductor substrate () is reduced, and the semiconductor substrate () is polished with improved center to edge uniformity. Since the semiconductor substrate () is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion () of the semiconductor substrate () are not over polished.

Polishing apparatus and method for forming an integrated circuit

A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

Extended poly buffer STI scheme

In one embodiment, a semiconductor substrate () is uniformly polished using a polishing pad () that has a first polishing region (), a second polishing region (), and a third polishing region (). The semiconductor substrate () is aligned to the polishing pad (), such that the center of the semiconductor substrate () overlies the second polishing region (), and the edge of the semiconductor substrate overlies the first polishing region () and the third polishing region (). During polishing, the semiconductor substrate () is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate (). This allows the semiconductor substrate () to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate () are not over polished.

A new method of forming shallow trench isolations using a reverse mask process is described. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches is etched through the etch stop layer and the polish stop layer into the substrate whereby narrow active areas and wide active areas of the substrate are left between the isolation trenches. An oxide layer is deposited over the etch stop layer and within the isolation trenches. The oxide layer is covered with a mask in the narrow active areas and in the isolation trenches and etched away in the wide active areas stopping at the etch stop layer. Thereafter, the mask is removed and the etch stop layer is polished away to the polish stop layer whereby the oxide layer in the isolation trenches is planarized.

Pre STI-CMP planarization scheme

A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish.

Method for buffer STI scheme with a hard mask layer as an oxidation barrier

A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing process removes the polysilicon layer and forms a plug of dielectric material that fills the trench. The plug of dielectric material has a top surface that is planar with respect to the top of the silicon nitride layer.

Shallow trench isolation using TEOS cap and polysilicon pullback

An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Intermetal dielectric layer for integrated circuits

An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

In one embodiment, a semiconductor substrate ( ) is uniformly polished using a polishing pad ( ) that has a first polishing region ( ), a second polishing region ( ), and a third polishing region ( ). The semiconductor substrate ( ) is aligned to the polishing pad ( ), such that the center of the semiconductor substrate ( ) overlies the second polishing region ( ), and the edge of the semiconductor substrate overlies the first polishing region ( ) and the third polishing region ( ). During polishing, the semiconductor substrate ( ) is not radially oscillated over the surface of the polishing pad, and as a result a more uniform polishing rate is achieved across the semiconductor substrate ( ). This allows the semiconductor substrate ( ) to be uniformly polished from center to edge, and increases die yield because die located on the semiconductor substrate ( ) are not over polished.

A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.

Method to prevent CU dishing during damascene formation

In one embodiment, a dielectric layer ( ) overlying a semiconductor substrate ( ) is uniformly polished. During polishing, the perimeter ( ) of the semiconductor substrate ( ) overlies a peripheral region ( ) of a polishing pad ( ) and an edge portion ( ) of the front surface of semiconductor substrate ( ) is not in contact with the front surface ( ) of the polishing pad ( ), in the peripheral region ( ). As a result, the polishing rate at the edge portion ( ) of the semiconductor substrate ( ) is reduced, and the semiconductor substrate ( ) is polished with improved center to edge uniformity. Since the semiconductor substrate ( ) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion ( ) of the semiconductor substrate ( ) are not over polished.

A new method of fabricating shallow trench isolations has been achieved. No final polishing down process is needed. A silicon substrate is provided. A pad oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer, the pad oxide layer, and the silicon substrate are patterned to form trenches for planned shallow trench isolations. A liner oxide layer is grown overlying the semiconductor substrate is the trenches. A silicon dioxide spacer layer is deposited overlying the silicon nitride layer and the liner oxide layer to partially fill the trenches. The silicon dioxide spacer layer and the liner oxide layer are anisotropically etched to form sidewall spacers inside the trenches and to expose the bottom of said trenches. A silicon layer is selectively grown overlying the semiconductor substrate in the trenches. The silicon layer partially fills the trenches. A trench oxide layer is formed overlying the silicon layer. The silicon nitride layer is removed. The pad oxide layer is removed to complete the shallow trench isolation, and the integrated circuit device is completed.

Method to form shallow trench isolations without a chemical mechanical polish

A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the FSG dielectric layer, comprising the following steps. A semiconductor structure having a metal structure, with an overlying liner layer, formed thereover is provided. A FSG dielectric layer is formed over the liner layer. The FSG dielectric layer having an exposed upper surface. The FSG dielectric layer is treated with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from the exposed surface of the FSG dielectric layer. A TEOS oxide layer is formed over the upper capping layer. The TEOS oxide layer is planarized to form a planarized TEOS oxide layer. The planarized TEOS oxide layer, the upper capping layer, the treated FSG dielectric layer, and the liner layer are patterned to form a via hole therethrough, exposing a portion of the metal structure and exposing sidewalls of the patterned treated FSG dielectric layer within the via opening. At least the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer within the via opening is treated with a second nitrogen gas/plasma treatment to form a fluorine depleted sidewall capping layer from the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer, wherein the upper and sidewall capping layers prevent the outgassing from the patterned FSG dielectric layer. A metal interconnect is formed within the via opening.

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Singapore, Singapore

Feng Chen