Lucent Technologies Inc.

Agere Systems Inc.

Feng Chen

Jiancheng Mo

Ravi Kumar Kolagotla

Hosahalli R Srinivas

Marc Stephen Diamondstein

Le Tieu Ly

David L Price

A digital filter or a receiver including a digital filter having at least two multiple stage shift registers. A plurality of multipliers corresponding in number to the number of stages in the at least two multiple stage shift registers receive as a first input an output from a corresponding stage of the at least two multiple stage shift registers. A tap weight shifter is coupled to a tap weight source to receive tap weights. The tap weight shifter is coupled to provide a second input to each multiplier. Each multiplier produces an output that is the product of inputs thereto. An adder sums the multiplier outputs to provide a sum output. The tap weight shifter then circularly shifts the tap weights and another multiply-add operation occurs. Several shift/multiply/add cycles may occur before data is again shifted into the at least two multiple stage shift registers, and another multiply-add operation occurs.

Receiver and low power digital filter therefor

A method for a cellular telephone receiver to detect the presence of a dotting sequence for a Manchester encoded cellular signal in a deep fading environment, wherein the presence of a single edge transition during the mask pulse for a predetermined number of consecutive clock cycles and the absence of any transition edges outside of the mask pulse for the predetermined number of consecutive clock cycles, indicate the presence of a dotting sequence and that the cellular receiver locked to a masked edge, thereby preventing the receiver from receiving the signal. In response, the receiver will shift the phase of its clock by 180 degrees so that it can lock to an unmasked edge of the cellular signal and thereby receive the signal. By contrast, the absence of any transition edges or the presence of more than one transition edge during the mask pulse indicates that the receiver is not receiving the cellular signal because of deep fading and not because it locked to a masked edge of the signal during the dotting sequence. In response, the receiver will not shift the phase of its clock, but will instead remain locked to an unmasked edge so that it can receive the cellular signal once the deep fading ceases.

Method for detecting a dotting sequence for manchester encoded data in a deep fading environment

A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively. A plurality of logic gates switches the clock output from the selected clock to the clock to next be selected by the clock select signal. A reset circuit turns off the clock drivers once the clock output has been switched from the selected clock to the clock to next be selected. The clock drivers for clocks that are not selected are turned off during and after the period of time the selected clock is switched to the clock to next be selected. Once the switching is complete, the entire clock switching circuit is turned off until another clock switching occurs.

Low power glitch-free clock switch

A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set. Accordingly, the flag generating circuit provides a race free and technology independent flag generating circuit capable of setting and resetting flags associated with asynchronous

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Bethlehem, PA, United States of America

Feng Chen