Intel Corporation

Semiconductor Manufacturing International (shanghai) Corporation

Molex Corporation

Zhejiang Hisun Pharmaceutical Co., Ltd.

Hewlett-packard Development Company, L.p.

Chinese Academy of Sciences

Paypal, Inc.

Semiconductor Manufacturing International (beijing) Corporation

Zhejiang Sanhua Intelligent Controls Co., Ltd.

Koninklijke Philips Corporation N.v.

Delta Electronics (shanghai) Co., Ltd

Intel Mobile Communications Gmbh

Opple Lighting Co., Ltd.

Semiconductor Manufacturing International Corp.

Zhejiang Sanhua Co., Ltd

Feng Chen

Altug Koker

Narayan Srinivasa

Abhishek R Appu

Joydeep Ray

Dukhwan Kim

Farshad Akhbari

Nadathur Rajagopalan Satish

Balaji Vembu

Kamal Sinha

Xiaoming Chen

Rajkishore Barik

Nicolas C Galoppo Von Borries

Prasoonkumar Surti

Eriko Nurvitadhi

Justin E Gottschlich

Linda L Hurd

Sara S Baghsorkhi

Tsung-Han Lin

Anbang Yao

Ben J Ashbaugh

John Charles Weast

Tatiana Shpeisman

Ping Tak Tang

Michael S Strickland

Mike B Macpherson

Travis T Schluessler

Subramaniam M Maiyuran

Vasanth Ranganathan

Sanjeev S Jahagirdar

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Wenyin Fu

Josh B Mastronarde

Jeremy Bottleson

Elmoustapha Ould-Ahmed-Vall

Chandrasekaran Sakthivel

Brian T Lewis

Murali Sundaresan

Liwei Ma

Kevin Nealis

Jeffrey R Jackson

Narayan Biswal

Zuoguo Wu

Stanley J Baran

Mike MacPherson

Gokcen Cilingir

Hua Bai

Nilesh V Shah

Barnan Das

Yang Liu

Archie Sharma

Mayuresh M Varerkar

Wenzhe Luo

Sherine Abdelhak

Paul Ouyang

Jong-Kae Fwu

Hujun Yin

RongZhen Yang

Thomas D Fletcher

Yuheng Zhang

Shandong Wang

Barath Lakshmanan

Ming Lu

Michael Mesnier

Li Xu

Mingqi Li

Sen Lin

Hong He

Mo-Han Fong

Youn Hyoung Heo

Umesh Phuyal

Xiaogang Chen

Yujian Zhang

Andreas Schmidt

Hyung-Nam Choi

Sanjay Dabral

Wei Zhou

David J Sager

Fei Li

Lei Zhang

Cheng Lu

Qiang Zhang

SeungHee Han

Yu Shen

Wei-Qiang Zhang

Ross Segelken

Feng Zhao

Xiaohan Yun

Hong-Yang Wu

Yiqi Wang

Hao Yin

Shahram Jamshidi

Jin Fu

Yang Yu

Chunliang Liu

Yaoliang Chen

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.

Training with adaptive runtime and precision profiling

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Techniques related to implementing and training image classification networks are discussed. Such techniques include applying shared convolutional layers to input images regardless of resolution and applying normalization selectively based on the input image resolution. Such techniques further include training using mixed image size parallel training and mixed image size ensemble distillation.

Input image size switchable network for adaptive runtime efficient image classification

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

A floating connector and an assembly thereof are provided. The floating connector includes: a center conductive structure which includes a main body, a contact pin which is movably mounted in a front portion of the main body and a center spring which is mounted between the contact pin and the main body, a rear portion of the main body is provided with a mating cavity, an elastic mating portion is provided in the mating cavity and is capable of elastically deforming in a radial direction which is perpendicular to a front-rear direction; an insulative body which surrounds an outer circumference of the center conductive structure; and an outer conductive structure comprising a first conductive shell which is provided to an outer circumference of the insulative body, a second conductive shell which is movable, and an outer spring which is positioned between the first conductive shell and the second conductive shell, at least one of the first conductive shell and the second conductive shell is provided with an elastic contact arm, and the first conductive shell and the second conductive shell maintain electrical contact via the elastic contact arm. The present disclosure can promote stability of electrical contact.

Floating connector and assembly thereof

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

A field-programmable gate array (FPGA)-based real-time processing system applied to underwater acoustic positioning and realizing reconfigurability and multiple output is provided. The system includes a multi-interface control and command parsing module for automatically completing sample information transmission and command parsing; a finite-state machine (FSM) of sample management for calculating related data and completing splitting, flipping and writing of a sample; a parallel correlation processor group for completing, in parallel, high-performance processing operations regarding a plurality of targets; and a multiple output data former for simultaneously realizing data formation of a multiple output result and outputting a flag bit signal to the outside. A FPGA-based real-time processing control method is also provided that is applied to underwater acoustic positioning and realizing reconfigurability and multiple output. The system and the method are used, such that during a whole realization process, under multiple array elements and multiple targets, high-speed parallel correlation processing is realized, thereby solving problems in terms of real-time performance, universality and anti-noise performance, and effectively realizing high-performance correlation.

FPGA-based real-time processing system and method applied to underwater acoustic positioning and realizing reconfigurability and multiple output

A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine an optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Tool for facilitating efficiency in machine learning

A floating connector and an assembly thereof are provided. The floating connector includes: a center conductive pin; an insulating seat which surrounds the center conductive pin; a mating side conductive shell which surrounds an outer periphery of the insulating seat; a movable conductive shell which is movably received in mating side conductive shell; an elastic element which elastically abuts against an upper end of the movable conductive shell; and an inner conductive shell which is interposed between the elastic element and the center conductive pin; the inner conductive shell has a fixing portion and a movable contacting portion, the fixing portion snaps on one of the mating side conductive shell and the movable conductive shell; the movable contacting portion slideably elastically abuts against the other of the mating side conductive shell and the movable conductive shell. In a vibration circumstance, a good electrical connection can be maintained and transmission quality of an electrical signal can also be promoted at the same time, which is particularly applicable to a situation of high frequency signal transmission.

Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

System and method for adapting executable object to a processing unit

Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

Adaptive deformable kernel prediction network for image de-noising

The present application provides an inductor framework and inductance device. The inductor framework includes a main winding part and an auxiliary winding part that are integrally arranged; the main winding part includes an upper end, a lower end, a main body, and an inserting hole; the main body is located between the upper end and the lower end, the inserting hole successively passes through the upper end, the main body, and the lower end in a direction from the top surface to the bottom surface; the auxiliary winding part extends from the lower end, a side surface of the auxiliary winding part facing away from the upper end is a welding surface; the auxiliary winding part is configured to be wound thereon an auxiliary coil that covers at least a portion of the welding surface, the auxiliary winding part is provided with a position limiting structure.

Inductor framework and inductance device

Growing community of inventors

Shanghai, China

Feng Chen