Intel Corporation

Fenardi Thenus

Peng Zou

Raghu Chepuri

Joseph T Dibene, Ii

Henry W Koertzen

Henry K Koertzen

David J Harriman

Sanjay Dabral

Zuoguo Wu

Joseph Dibene Ii

In some embodiments described herein, proposed schemes utilize a duty-cycle sensing technique to detect load current imbalance in each individual inductor, and then adjusts the duty cycles for the specific phases through a digital duty cycle tuner.

Method and apparatus of current balancing for multiple phase power converter

An apparatus comprises a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL to sample the second output with the first output and to generate a pulse-frequency modulation (PFM) output. A voltage regulator comprises mutually coupled on-die inductors for coupling to a load; a bridge coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising a comparator and a first PDL coupled to the comparator.

Low power high frequency digital pulse frequency modulator

Described is a soft-start scheme for a voltage regulator. The apparatus comprises: a first voltage regulator to provide regulated voltage to an output node coupled to a load, the first voltage regulator operable to be in open loop via a bypass unit, the first voltage regulator including a comparator; and a second voltage regulator, coupled to the first voltage regulator, operable to be in closed loop, via the bypass unit, to provide a reference voltage for the comparator of the first voltage regulator.

Apparatus for starting up switching voltage regulator

Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.

In one embodiment, a test apparatus includes a field programmable gate array (FPGA) including a first transmitter to communicate first signals according to current mode logic (CML) signaling and a first receiver to receive second signals according to the CML signaling, and an interface circuit to couple the FPGA to a device that is to communicate according to voltage mode signaling. The interface circuit may adapt the first signals communicated by the first transmitter according to the CML signaling to voltage mode signaling signals for receipt by the device. Other embodiments are described and claimed.

Interface circuitry for a test apparatus

Embodiments of an apparatus, system and method are described for dynamically time-interleaving supply voltage modulation to shape a power profile. An apparatus may comprise, for example, a power management module to monitor power information received from a plurality of devices and send a power control signal including delay information to each device having power information that exceeds a power threshold, the delay information comprising information for time-interleaving power usage among the devices having power information that exceeds the power threshold. Other embodiments are described and claimed.

Method and apparatus for power profile shaping using time-interleaved voltage modulation

Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.

Growing community of inventors

Portland, OR, United States of America

Fenardi Thenus