National Semiconductor Corporation

Felix C Li

Jaime A Bayan

Lee Han Meng@Eugene Lee

Santhiran Nadarajah

Peng Soon Lim

Ah Lek Hu

Terh Kuen Yii

Yee Kim Lee

A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an 'up-set' bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Delamination resistant device package having raised bond surface and mold locking aperture

A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features 'up-set' bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity. Such packages can be constructed in single inline configuration, dual inline configuration, quad package configurations.

Delamination resistant device package having low moisture sensitivity

A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at least one peripheral side edge of the die.

I/O pad structures for integrated circuit devices

One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described.

Packaging integrated circuits for high stress environments

A semiconductor device is provided, which comprises: a die including an active surface; a multiplicity of bond pads formed on the active surface of the die, wherein a first one of the bond pads is larger than a second one of the bond pads; and a multiplicity of solder bumps, each formed over a corresponding bond pad, wherein the multiplicity of solder bumps include a first solder bump formed over the first bond pad and a second solder bump formed over the second bond pad, the first solder bump having a footprint that is substantially larger than the second solder bump and a maximum diameter that is substantially larger than the second solder bump.

Power micro surface-mount device package

An apparatus and method for forming a substantially continuous solder bump around the periphery of each dice on a flip chip wafer is disclosed. The solder bump is provided on each die so that when it is singulated from the wafer and mounted onto a substrate, the solder bump around the periphery acts to hermetically attach and seal the die to the substrate. According to various embodiments of the invention, the continuous solder bump may be coupled to either a ground plane or a power supply on the substrate. The method includes fabricating a plurality of integrated circuit dice on a first surface of a semiconductor wafer. After the integrated circuitry is fabricated, a substantially continuous solder bump is formed on the periphery of each of the dice on the wafer.

Apparatus and method for forming solder seals for semiconductor flip chip packages

A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at least one peripheral side edge of the die. Solder fillets are formed between the extended I/O pads and corresponding contacts on a substrate.

Integrated circuit package

A semiconductor package is provided with an internal package formed in the cavity of the external leadless leadframe package (LLP). The internal package is a leadless leadframe package and provides a substrate for mounting one or more die and passive devices to form the external LLP. By arranging the die and passive components on the internal package, higher chip density and a smaller form factor may be achieved.

Leadless leadframe package substitute and stack package

An apparatus and method for an enhanced thermally conductive package for high powered semiconductor devices. The package includes a semiconductor die having an active surface and a non-active surface and a metal layer formed on the non-active surface of the die. The package is intended to be mounted onto a metal pad provided on a printed circuit board. A solder is used to affix the metal layer on the non-active surface of the die to the metal pad of the printed circuit board. The interface between the die and the printed circuit board thus includes just three metal layers, including the non-active surface of the die, the solder, and the metal pad on the printed circuit board. The reduced number of metal layers improves heat dissipation and thermal conductivity of the package.

Apparatus and method for enhanced thermal conductivity packages for high powered semiconductor devices

Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.

Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)

A substrate for use in an inline IC package is designed such that its die attach pad and leads each have a number of protrusions and recesses. These protrusions and recesses create an irregular surface that provides better adhesion to encapsulant material than conventional leads and die attach pads, whose smooth, straight surfaces risk delamination of the encapsulant material.

Growing community of inventors

San Jose, CA, United States of America

Felix C Li