Xilinx, Inc.

Wind River Systems, Inc.

Felix Burton

Ahmad R Ansari

David P Schultz

Maarten Koning

James D Wesselkamper

Sandeep Dutta

Andrew Gaiarsa

Krishna C Patakamuri

Peder C Andersen

Jeffrey Cuppett

Henry C Yu

Ming-dong Chen

Mitch Stanek

Ming-Dong Chen

Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

Register integrity check in configurable devices

Techniques to update firmware without a system reset include preserving state information associated with one or more firmware services, suspending processing of firmware service requests, loading an updated firmware image, and resuming processing of firmware service requests based on the preserved state information and the updated firmware image. Unpreserved states of one or more other firmware services may be recreated upon resumption of processing of the firmware service requests.

Impactless firmware update

Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H, and a first data chunk C. Signature S may be signed on a first hash H. Hmay be the hash for Hand C. If signature S passes verification, a hash engine may perform hash functions on Cand Hto generate a hash H'. H&#x2032; may be compared with Hto indicate whether Chas been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes H, H, and a data chunk C, or, a signature S, a hash H, and a data chunk C.

Incremental authentication for memory constrained systems

An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.

Common input/output interface for application and debug circuitry

A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

Debug controller circuit

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

System and method for operating system aware low latency interrupt handling

Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system

A method for extracting static information from user code, analyzing the static information to determine location expressions for program information and comparing the location expressions to reference location expressions of the user code. In addition, a system having a reading module configured to read and extract static information from user code, an analyzing module configured to analyze the static information to determine location expressions for program information and a comparison module configured to compare the location expressions to reference location expressions of the user code.

System and method for stack crawl testing and caching

A system and method for executing application code in an operating system environment, attaching a development tool to the application code, saving a state of the application code, determining whether the attachment of the development tool interrupted a blocking system call of the application code, modifying, when it is determined the attachment of the development tool interrupted the blocking system call, the saved state to a further saved state corresponding to restarting the blocking system call and restoring the state of the application code to the further saved state.

Method and system for improved tool interaction with a target

A method for memory reclamation is disclosed that includes marking a memory object when an attempt to alter a reference to the memory object is detected by a software write barrier. Marking be by using representations ('black,' 'white', &#x201c;gray&#x201d;) stored as part of a garbage collection information data structure associated with each memory object. Initially, all allocated memory objects are marked white. Objects are then processed such that objects referenced by pointers are marked gray. Each object marked gray is then processed to determine objects referenced by pointers in it, and such objects are marked gray. When all objects referenced by pointers in the selected gray objected have been processed, the selected gray object is marked black. When all processing has been completed, objects still marked white may be reclaimed. Also described is a garbage collector which runs as a task concurrently with other tasks. A priority of the garbage collector may be increased to prevent interruption during certain parts of the garbage collection procedure.

Growing community of inventors

Foster City, CA, United States of America

Felix Burton